Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1521,7 +1521,8 @@
 
 static bool shouldEmitGOTReloc(const GlobalValue *GV,
                                const TargetMachine &TM) {
-  return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+  return (GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
+            GV->hasLinkOnceLinkage() || GV->hasLinkOnceODRLinkage()) &&
          !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
 }
 
Index: test/CodeGen/AMDGPU/global-variable-relocs.ll
===================================================================
--- test/CodeGen/AMDGPU/global-variable-relocs.ll
+++ test/CodeGen/AMDGPU/global-variable-relocs.ll
@@ -4,10 +4,12 @@
 @internal = internal addrspace(1) global [256 x i32] zeroinitializer
 @available_externally = available_externally addrspace(1) global [256 x i32] zeroinitializer
 @linkonce = linkonce addrspace(1) global [256 x i32] zeroinitializer
+@linkonce_const = linkonce addrspace(2) constant [256 x i32] zeroinitializer
 @weak= weak addrspace(1) global [256 x i32] zeroinitializer
 @common = common addrspace(1) global [256 x i32] zeroinitializer
 @extern_weak = extern_weak addrspace(1) global [256 x i32]
 @linkonce_odr = linkonce_odr addrspace(1) global [256 x i32] zeroinitializer
+@linkonce_odr_const = linkonce_odr addrspace(2) constant [256 x i32] zeroinitializer
 @weak_odr = weak_odr addrspace(1) global [256 x i32] zeroinitializer
 @external = external addrspace(1) global [256 x i32]
 @external_w_init = addrspace(1) global [256 x i32] zeroinitializer
@@ -74,6 +76,21 @@
   ret void
 }
 
+; CHECK-LABEL: linkonce_const_test:
+; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_const@GOTPCREL+4
+; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
+; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
+define void @linkonce_const_test(i32 addrspace(1)* %out) {
+entry:
+  %0 = load i32, i32 addrspace(1)* %out, align 4
+  %1 = sext i32 %0 to i64
+  %arrayidx1 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(2)* @linkonce_const, i64 0, i64 %1
+  %2 = load i32, i32 addrspace(2)* %arrayidx1, align 4
+  store i32 %2, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; CHECK-LABEL: weak_test:
 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@GOTPCREL+4
@@ -142,6 +159,21 @@
   ret void
 }
 
+; CHECK-LABEL: linkonce_odr_const_test:
+; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_odr_const@GOTPCREL+4
+; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
+; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
+define void @linkonce_odr_const_test(i32 addrspace(1)* %out) {
+entry:
+  %0 = load i32, i32 addrspace(1)* %out, align 4
+  %1 = sext i32 %0 to i64
+  %arrayidx1 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(2)* @linkonce_odr_const, i64 0, i64 %1
+  %2 = load i32, i32 addrspace(2)* %arrayidx1, align 4
+  store i32 %2, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; CHECK-LABEL: weak_odr_test:
 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak_odr@GOTPCREL+4