Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -4365,6 +4365,7 @@
                                               SelectionDAG &DAG) const {
   unsigned Reg = StringSwitch<unsigned>(RegName)
                        .Case("sp", ARM::SP)
+                       .Case("pc", ARM::PC)
                        .Default(0);
   if (Reg)
     return Reg;
Index: test/CodeGen/ARM/named-reg-alloc2.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/named-reg-alloc2.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
+
+define i32 @get_stack() nounwind {
+entry:
+; CHECK: mov r0, sp
+	%sp = call i32 @llvm.read_register.i32(metadata !0)
+  ret i32 %sp
+}
+
+define i32 @get_pc() nounwind {
+entry:
+; CHECK: mov r0, pc
+	%sp = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %sp
+}
+
+declare i32 @llvm.read_register.i32(metadata) nounwind
+
+!0 = !{!"sp\00"}
+!1 = !{!"pc\00"}