Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -613,6 +613,11 @@
     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
   }
+
+  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
+  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
+  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
+  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
 }
 
 // This is supposed to be log2(Size)
Index: llvm/trunk/lib/Target/AMDGPU/SIDefines.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIDefines.h
+++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h
@@ -308,5 +308,7 @@
 #define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
 #define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
 
+#define R_SPILLED_SGPRS         0x4
+#define R_SPILLED_VGPRS         0x8
 
 #endif
Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -85,6 +85,9 @@
   bool HasNonSpillStackObjects;
   bool HasFlatInstructions;
 
+  unsigned NumSpilledSGPRs;
+  unsigned NumSpilledVGPRs;
+
   // Feature bits required for inputs passed in user SGPRs.
   bool PrivateSegmentBuffer : 1;
   bool DispatchPtr : 1;
@@ -313,6 +316,22 @@
     HasFlatInstructions = UseFlat;
   }
 
+  unsigned getNumSpilledSGPRs() const {
+    return NumSpilledSGPRs;
+  }
+
+  unsigned getNumSpilledVGPRs() const {
+    return NumSpilledVGPRs;
+  }
+
+  void addToSpilledSGPRs(unsigned num) {
+    NumSpilledSGPRs += num;
+  }
+
+  void addToSpilledVGPRs(unsigned num) {
+    NumSpilledVGPRs += num;
+  }
+
   unsigned getPSInputAddr() const {
     return PSInputAddr;
   }
Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -63,6 +63,8 @@
     HasSpilledVGPRs(false),
     HasNonSpillStackObjects(false),
     HasFlatInstructions(false),
+    NumSpilledSGPRs(0),
+    NumSpilledVGPRs(0),
     PrivateSegmentBuffer(false),
     DispatchPtr(false),
     QueuePtr(false),
Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -573,6 +573,7 @@
         }
       }
       MI->eraseFromParent();
+      MFI->addToSpilledSGPRs(NumSubRegs);
       break;
     }
 
@@ -642,6 +643,7 @@
             FrameInfo->getObjectOffset(Index) +
             TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
       MI->eraseFromParent();
+      MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
       break;
     case AMDGPU::SI_SPILL_V32_RESTORE:
     case AMDGPU::SI_SPILL_V64_RESTORE: