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Differential D22191

[AARCH64] Enable AARCH64 lit tests on windows dev machines
ClosedPublic

Authored by RKSimon on Jul 9 2016, 3:55 PM.

Details

Reviewers
spatel
rengolin
filcab
jmolloy
chapuni
Commits
rGfc4d4b251db5: [AARCH64] Enable AARCH64 lit tests on windows dev machines
rL275973: [AARCH64] Enable AARCH64 lit tests on windows dev machines
Summary

As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows

This will hopefully help stop cases where windows developers break the aarch64 target

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 63403.Jul 9 2016, 3:55 PM
RKSimon retitled this revision from to [AARCH64] Enable AARCH64 lit tests on windows dev machines.
RKSimon updated this object.
RKSimon added reviewers: jmolloy, chapuni, filcab, spatel.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptJul 9 2016, 3:56 PM
davide added a subscriber: davide.Jul 9 2016, 3:58 PM
filcab edited edge metadata.Jul 12 2016, 3:53 AM

Thanks for working on this!

test/CodeGen/AArch64/aarch64-minmaxv.ll
1 ↗(On Diff #63403)

I randomly saw this "linu". It looks like a typo and can probably be changed to Linux.

rengolin added a comment.Jul 19 2016, 4:21 AM

This looks like a good idea, have you ran the test on Linux after the change?

test/CodeGen/AArch64/aarch64-minmaxv.ll
1 ↗(On Diff #63403)

This seems the only occurrence, as it was a typo in the original triple. :)

RKSimon added a comment.Jul 19 2016, 4:23 AM
In D22191#488090, @rengolin wrote:

This looks like a good idea, have you ran the test on Linux after the change?

No, just windows and OSX - good enough?

test/CodeGen/AArch64/aarch64-minmaxv.ll
1 ↗(On Diff #63403)

I can fix this post.

rengolin added a comment.Jul 19 2016, 4:24 AM
In D22191#488092, @RKSimon wrote:

No, just windows and OSX - good enough?

I can try this one quickly locally. BRB. :)

rengolin added a comment.Jul 19 2016, 4:41 AM

Just found out you have Windows line endings on your patch. Please make sure they're not committed in.

rengolin accepted this revision.Jul 19 2016, 5:26 AM
rengolin added a reviewer: rengolin.

Works on Linux, too. Just make sure to remove the Windows line endings and replace linu for linux. Thanks!

This revision is now accepted and ready to land.Jul 19 2016, 5:26 AM
Closed by commit rL275973: [AARCH64] Enable AARCH64 lit tests on windows dev machines (authored by RKSimon). · Explain WhyJul 19 2016, 7:09 AM
This revision was automatically updated to reflect the committed changes.
RKSimon mentioned this in rL275976: [AARCH64] Fix linu triple typo.Jul 19 2016, 7:20 AM

Revision Contents

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AArch64/
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Diff 64489

llvm/trunk/test/CodeGen/AArch64/Redundantstore.ll

; RUN: llc -O3 -march=aarch64 < %s | FileCheck %s ; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@end_of_array = common global i8* null, align 8 @end_of_array = common global i8* null, align 8
; CHECK-LABEL: @test ; CHECK-LABEL: @test
; CHECK: stur ; CHECK: stur
; CHECK-NOT: stur ; CHECK-NOT: stur
define i8* @test(i32 %size) { define i8* @test(i32 %size) {
Show All 16 Lines

llvm/trunk/test/CodeGen/AArch64/aarch64-DAGCombine-findBetterNeighborChains-crash.ll

; RUN: llc < %s -march=arm64 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu
; Make sure we are not crashing on this test. ; Make sure we are not crashing on this test.
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
declare void @extern(i8*) declare void @extern(i8*)
; Function Attrs: argmemonly nounwind ; Function Attrs: argmemonly nounwind
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @func(float* noalias %arg, i32* noalias %arg1, i8* noalias %arg2, i8* noalias %arg3) #1 { define void @func(float* noalias %arg, i32* noalias %arg1, i8* noalias %arg2, i8* noalias %arg3) #1 {
Show All 30 Lines

llvm/trunk/test/CodeGen/AArch64/aarch64-addv.ll

; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic < %s | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s
define i8 @add_B(<16 x i8>* %arr) { define i8 @add_B(<16 x i8>* %arr) {
; CHECK-LABEL: add_B ; CHECK-LABEL: add_B
; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b ; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
%bin.rdx = load <16 x i8>, <16 x i8>* %arr %bin.rdx = load <16 x i8>, <16 x i8>* %arr
%rdx.shuf0 = shufflevector <16 x i8> %bin.rdx, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %rdx.shuf0 = shufflevector <16 x i8> %bin.rdx, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx0 = add <16 x i8> %bin.rdx, %rdx.shuf0 %bin.rdx0 = add <16 x i8> %bin.rdx, %rdx.shuf0
%rdx.shuf = shufflevector <16 x i8> %bin.rdx0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef > %rdx.shuf = shufflevector <16 x i8> %bin.rdx0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef >
▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/aarch64-minmaxv.ll

; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic < %s | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linu--gnu -aarch64-neon-syntax=generic | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linu--gnu"
; CHECK-LABEL: smax_B ; CHECK-LABEL: smax_B
; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b ; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
define i8 @smax_B(<16 x i8>* nocapture readonly %arr) { define i8 @smax_B(<16 x i8>* nocapture readonly %arr) {
%arr.load = load <16 x i8>, <16 x i8>* %arr %arr.load = load <16 x i8>, <16 x i8>* %arr
%rdx.shuf = shufflevector <16 x i8> %arr.load, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %rdx.shuf = shufflevector <16 x i8> %arr.load, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%rdx.minmax.cmp22 = icmp sgt <16 x i8> %arr.load, %rdx.shuf %rdx.minmax.cmp22 = icmp sgt <16 x i8> %arr.load, %rdx.shuf
%rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %arr.load, <16 x i8> %rdx.shuf %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %arr.load, <16 x i8> %rdx.shuf
▲ Show 20 Lines • Show All 499 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define void @foo(i64 %val) { define void @foo(i64 %val) {
; CHECK: foo ; CHECK: foo
; The stack frame store is not 64-bit aligned. Make sure we use an ; The stack frame store is not 64-bit aligned. Make sure we use an
; instruction that can handle that. ; instruction that can handle that.
; CHECK: stur x0, [sp, #20] ; CHECK: stur x0, [sp, #20]
%a = alloca [49 x i32], align 4 %a = alloca [49 x i32], align 4
%p32 = getelementptr inbounds [49 x i32], [49 x i32]* %a, i64 0, i64 2 %p32 = getelementptr inbounds [49 x i32], [49 x i32]* %a, i64 0, i64 2
%p = bitcast i32* %p32 to i64* %p = bitcast i32* %p32 to i64*
store i64 %val, i64* %p, align 8 store i64 %val, i64* %p, align 8
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll

; RUN: llc < %s -march=arm64 ; RUN: llc < %s -mtriple=arm64-eabi
; The target lowering for integer comparisons was replacing some DAG nodes ; The target lowering for integer comparisons was replacing some DAG nodes
; during operation legalization, which resulted in dangling pointers, ; during operation legalization, which resulted in dangling pointers,
; cycles in DAGs, and eventually crashes. This is the testcase for ; cycles in DAGs, and eventually crashes. This is the testcase for
; one of those crashes. (rdar://10653656) ; one of those crashes. (rdar://10653656)
define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 { define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 {
entry: entry:
Show All 31 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define i32 @foo(<4 x i32> %a, i32 %n) nounwind { define i32 @foo(<4 x i32> %a, i32 %n) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: fmov w0, s0 ; CHECK: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = bitcast <4 x i32> %a to i128 %b = bitcast <4 x i32> %a to i128
%c = trunc i128 %b to i32 %c = trunc i128 %b to i32
ret i32 %c ret i32 %c
Show All 11 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll

; RUN: llc < %s -march arm64 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
; <rdar://problem/11294426> ; <rdar://problem/11294426>
@b = private unnamed_addr constant [3 x i32] [i32 1768775988, i32 1685481784, i32 1836253201], align 4 @b = private unnamed_addr constant [3 x i32] [i32 1768775988, i32 1685481784, i32 1836253201], align 4
; The important thing for this test is that we need an unaligned load of `l_b' ; The important thing for this test is that we need an unaligned load of `l_b'
; ("ldr w2, [x1, #8]" in this case). ; ("ldr w2, [x1, #8]" in this case).
; CHECK: adrp x[[PAGE:[0-9]+]], {{l_b@PAGE|.Lb}} ; CHECK: adrp x[[PAGE:[0-9]+]], {{l_b@PAGE|.Lb}}
Show All 12 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll

; RUN: llc -march=arm64 -O0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -O0 -verify-machineinstrs | FileCheck %s
; RUN: llc -march=arm64 -O3 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -O3 -verify-machineinstrs | FileCheck %s
@.str = private unnamed_addr constant [9 x i8] c"%lf %lu\0A\00", align 1 @.str = private unnamed_addr constant [9 x i8] c"%lf %lu\0A\00", align 1
@.str1 = private unnamed_addr constant [8 x i8] c"%lf %u\0A\00", align 1 @.str1 = private unnamed_addr constant [8 x i8] c"%lf %u\0A\00", align 1
@.str2 = private unnamed_addr constant [8 x i8] c"%f %lu\0A\00", align 1 @.str2 = private unnamed_addr constant [8 x i8] c"%f %lu\0A\00", align 1
@.str3 = private unnamed_addr constant [7 x i8] c"%f %u\0A\00", align 1 @.str3 = private unnamed_addr constant [7 x i8] c"%f %u\0A\00", align 1
define void @testDouble(double %d) ssp { define void @testDouble(double %d) ssp {
; CHECK-LABEL: testDouble: ; CHECK-LABEL: testDouble:
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -aarch64-neon-syntax=apple -fp-contract=fast | FileCheck %s --check-prefix=FAST
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
;FAST-LABEL: _Z9example25v: ;FAST-LABEL: _Z9example25v:
;FAST: fcmgt.4s ;FAST: fcmgt.4s
;FAST: ret ;FAST: ret
;CHECK-LABEL: _Z9example25v: ;CHECK-LABEL: _Z9example25v:
;CHECK: fcmgt.4s ;CHECK: fcmgt.4s
;CHECK: ret ;CHECK: ret
define <4 x i32> @_Z9example25v( <4 x float> %N0, <4 x float> %N1) { define <4 x i32> @_Z9example25v( <4 x float> %N0, <4 x float> %N1) {
%A = fcmp olt <4 x float> %N0, %N1 %A = fcmp olt <4 x float> %N0, %N1
%B = zext <4 x i1> %A to <4 x i32> %B = zext <4 x i1> %A to <4 x i32>
ret <4 x i32> %B ret <4 x i32> %B
} }

llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll

; RUN: llc < %s -march=arm64 ; RUN: llc < %s -mtriple=arm64-eabi
; Make sure we are not crashing on this test. ; Make sure we are not crashing on this test.
define void @autogen_SD13158() { define void @autogen_SD13158() {
entry: entry:
%B26 = frem float 0.000000e+00, undef %B26 = frem float 0.000000e+00, undef
br i1 undef, label %CF, label %CF77 br i1 undef, label %CF, label %CF77
CF: ; preds = %CF, %CF76 CF: ; preds = %CF, %CF76
store float %B26, float* undef store float %B26, float* undef
br i1 undef, label %CF, label %CF77 br i1 undef, label %CF, label %CF77
CF77: ; preds = %CF CF77: ; preds = %CF
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll

; RUN: llc < %s -march=arm64 ; RUN: llc < %s -mtriple=arm64-eabi
; Make sure we are not crashing on this test. ; Make sure we are not crashing on this test.
define void @autogen_SD12881() { define void @autogen_SD12881() {
BB: BB:
%B17 = ashr <4 x i32> zeroinitializer, zeroinitializer %B17 = ashr <4 x i32> zeroinitializer, zeroinitializer
br label %CF br label %CF
Show All 28 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple
;CHECK-LABEL: Shuff: ;CHECK-LABEL: Shuff:
;CHECK: tbl.8b ;CHECK: tbl.8b
;CHECK: ret ;CHECK: ret
define <8 x i8 > @Shuff(<8 x i8> %in, <8 x i8>* %out) nounwind ssp { define <8 x i8 > @Shuff(<8 x i8> %in, <8 x i8>* %out) nounwind ssp {
%value = shufflevector <8 x i8> %in, <8 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> %value = shufflevector <8 x i8> %in, <8 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %value ret <8 x i8> %value
} }

llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT
; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT
; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT
; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT
define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: add.2d v[[REG:[0-9]+]], v0, v1 ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1
; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1
; Without advanced copy optimization, we end up with cross register ; Without advanced copy optimization, we end up with cross register
; banks copies that cannot be coalesced. ; banks copies that cannot be coalesced.
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llvm/trunk/test/CodeGen/AArch64/arm64-AnInfiniteLoopInDAGCombine.ll

; RUN: llc < %s -march=arm64 ; RUN: llc < %s -mtriple=arm64-eabi
; This test case tests an infinite loop bug in DAG combiner. ; This test case tests an infinite loop bug in DAG combiner.
; It just tries to do the following replacing endlessly: ; It just tries to do the following replacing endlessly:
; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4] ; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4] ; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
; ;
; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4] ; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4] ; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
; an optimization to replace unused bits with undefined bits, we remove ; an optimization to replace unused bits with undefined bits, we remove
; the (1) optimization (It doesn't make sense to replace undefined bits ; the (1) optimization (It doesn't make sense to replace undefined bits
; with signed bits). ; with signed bits).
define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) { define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) {
entry: entry:
%cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768> %cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768>
%sext.i = sext <4 x i1> %cmp.i to <4 x i32> %sext.i = sext <4 x i1> %cmp.i to <4 x i32>
%mul.i = mul <4 x i32> %in0, %sext.i %mul.i = mul <4 x i32> %in0, %sext.i
%sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16> %sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16>
%vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16> %vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %vmovl.i.i ret <4 x i32> %vmovl.i.i
} }
No newline at end of file No newline at end of file

llvm/trunk/test/CodeGen/AArch64/arm64-EXT-undef-mask.ll

; RUN: llc -O0 -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s
; The following 2 test cases test shufflevector with beginning UNDEF mask. ; The following 2 test cases test shufflevector with beginning UNDEF mask.
define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) { define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
;CHECK-LABEL: test_vext_undef_traverse: ;CHECK-LABEL: test_vext_undef_traverse:
;CHECK: {{ext.16b.*v0, #4}} ;CHECK: {{ext.16b.*v0, #4}}
%vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9> %vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
ret <8 x i16> %vext ret <8 x i16> %vext
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
target triple = "arm64-apple-ios7.0.0"
; rdar://13625505 ; rdar://13625505
; Here we have 9 fixed integer arguments the 9th argument in on stack, the ; Here we have 9 fixed integer arguments the 9th argument in on stack, the
; varargs start right after at 8-byte alignment. ; varargs start right after at 8-byte alignment.
define void @fn9(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp { define void @fn9(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
; CHECK-LABEL: fn9: ; CHECK-LABEL: fn9:
; 9th fixed argument ; 9th fixed argument
; CHECK: ldr {{w[0-9]+}}, [sp, #64] ; CHECK: ldr {{w[0-9]+}}, [sp, #64]
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llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false -disable-fp-elim | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false -disable-fp-elim | FileCheck %s
; RUN: llc < %s -O0 -disable-fp-elim | FileCheck -check-prefix=FAST %s ; RUN: llc < %s -mtriple=arm64-apple-darwin -O0 -disable-fp-elim | FileCheck -check-prefix=FAST %s
target triple = "arm64-apple-darwin"
; rdar://12648441 ; rdar://12648441
; Generated from arm64-arguments.c with -O2. ; Generated from arm64-arguments.c with -O2.
; Test passing structs with size < 8, < 16 and > 16 ; Test passing structs with size < 8, < 16 and > 16
; with alignment of 16 and without ; with alignment of 16 and without
; Structs with size < 8 ; Structs with size < 8
%struct.s38 = type { i32, i16 } %struct.s38 = type { i32, i16 }
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llvm/trunk/test/CodeGen/AArch64/arm64-addp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
define double @foo(<2 x double> %a) nounwind { define double @foo(<2 x double> %a) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: faddp.2d d0, v0 ; CHECK: faddp.2d d0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%lane0.i = extractelement <2 x double> %a, i32 0 %lane0.i = extractelement <2 x double> %a, i32 0
%lane1.i = extractelement <2 x double> %a, i32 1 %lane1.i = extractelement <2 x double> %a, i32 1
%vpaddd.i = fadd double %lane0.i, %lane1.i %vpaddd.i = fadd double %lane0.i, %lane1.i
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llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll

; RUN: llc -march arm64 < %s -aarch64-collect-loh=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-collect-loh=false | FileCheck %s
; rdar://13452552 ; rdar://13452552
; Disable the collecting of LOH so that the labels do not get in the ; Disable the collecting of LOH so that the labels do not get in the
; way of the NEXT patterns. ; way of the NEXT patterns.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios3.0.0"
@block = common global i8* null, align 8 @block = common global i8* null, align 8
define zeroext i8 @fullGtU(i32 %i1, i32 %i2) { define zeroext i8 @fullGtU(i32 %i1, i32 %i2) {
; CHECK: fullGtU ; CHECK: fullGtU
; CHECK: adrp [[PAGE:x[0-9]+]], _block@GOTPAGE ; CHECK: adrp [[PAGE:x[0-9]+]], _block@GOTPAGE
; CHECK: ldr [[ADDR:x[0-9]+]], {{\[}}[[PAGE]], _block@GOTPAGEOFF] ; CHECK: ldr [[ADDR:x[0-9]+]], {{\[}}[[PAGE]], _block@GOTPAGEOFF]
; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]] ; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]]
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llvm/trunk/test/CodeGen/AArch64/arm64-addrmode.ll

; RUN: llc -march=arm64 < %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi < %s | FileCheck %s
; rdar://10232252 ; rdar://10232252
@object = external hidden global i64, section "__DATA, __objc_ivar", align 8 @object = external hidden global i64, section "__DATA, __objc_ivar", align 8
; base + offset (imm9) ; base + offset (imm9)
; CHECK: @t1 ; CHECK: @t1
; CHECK: ldr xzr, [x{{[0-9]+}}, #8] ; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
; CHECK: ret ; CHECK: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll

; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi -mcpu=cyclone < %s | FileCheck %s
; CHECK: foo ; CHECK: foo
; CHECK: str w[[REG0:[0-9]+]], [x19, #264] ; CHECK: str w[[REG0:[0-9]+]], [x19, #264]
; CHECK: mov w[[REG1:[0-9]+]], w[[REG0]] ; CHECK: mov w[[REG1:[0-9]+]], w[[REG0]]
; CHECK: str w[[REG1]], [x19, #132] ; CHECK: str w[[REG1]], [x19, #132]
define i32 @foo(i32 %a) nounwind { define i32 @foo(i32 %a) nounwind {
%retval = alloca i32, align 4 %retval = alloca i32, align 4
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llvm/trunk/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll

; RUN: llc -O1 -march=arm64 -enable-andcmp-sinking=true < %s | FileCheck %s ; RUN: llc -O1 -mtriple=arm64-apple-ios7.0.0 -enable-andcmp-sinking=true < %s | FileCheck %s
; ModuleID = 'and-cbz-extr-mr.bc' ; ModuleID = 'and-cbz-extr-mr.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 { define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
; CHECK: _foo: ; CHECK: _foo:
entry: entry:
%tobool = icmp eq i8* %str14, null %tobool = icmp eq i8* %str14, null
br i1 %tobool, label %return, label %if.end br i1 %tobool, label %return, label %if.end
; CHECK: %if.end ; CHECK: %if.end
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llvm/trunk/test/CodeGen/AArch64/arm64-arith-saturating.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp { define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: qadds: ; CHECK-LABEL: qadds:
; CHECK: sqadd s0, s0, s1 ; CHECK: sqadd s0, s0, s1
%vecext = extractelement <4 x i32> %b, i32 0 %vecext = extractelement <4 x i32> %b, i32 0
%vecext1 = extractelement <4 x i32> %c, i32 0 %vecext1 = extractelement <4 x i32> %c, i32 0
%vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
ret i32 %vqadd.i ret i32 %vqadd.i
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llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll

; RUN: llc < %s -march=arm64 -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false | FileCheck %s
define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp { define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: add w0, w1, w0 ; CHECK: add w0, w1, w0
; CHECK: ret ; CHECK: ret
%add = add i32 %b, %a %add = add i32 %b, %a
ret i32 %add ret i32 %add
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llvm/trunk/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll

; RUN: llc -march=arm64 -aarch64-dead-def-elimination=false < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-ios7.0.0 -aarch64-dead-def-elimination=false < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define i32 @test1() #0 { define i32 @test1() #0 {
%tmp1 = alloca i8 %tmp1 = alloca i8
%tmp2 = icmp eq i8* %tmp1, null %tmp2 = icmp eq i8* %tmp1, null
%tmp3 = zext i1 %tmp2 to i32 %tmp3 = zext i1 %tmp2 to i32
ret i32 %tmp3 ret i32 %tmp3
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
; CHECK: adds {{x[0-9]+}}, sp, #15 ; CHECK: adds {{x[0-9]+}}, sp, #15
} }

llvm/trunk/test/CodeGen/AArch64/arm64-atomic-128.ll

; RUN: llc < %s -march=arm64 -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
@var = global i128 0 @var = global i128 0
define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) { define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
; CHECK-LABEL: val_compare_and_swap: ; CHECK-LABEL: val_compare_and_swap:
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[RESULTLO:x[0-9]+]], [[RESULTHI:x[0-9]+]], [x[[ADDR:[0-9]+]]] ; CHECK: ldaxp [[RESULTLO:x[0-9]+]], [[RESULTHI:x[0-9]+]], [x[[ADDR:[0-9]+]]]
; CHECK-DAG: eor [[MISMATCH_LO:x[0-9]+]], [[RESULTLO]], x2 ; CHECK-DAG: eor [[MISMATCH_LO:x[0-9]+]], [[RESULTLO]], x2
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llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll

; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 { define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
; CHECK-LABEL: val_compare_and_swap: ; CHECK-LABEL: val_compare_and_swap:
; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]: ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]] ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
; CHECK-NEXT: cmp [[RESULT]], w1 ; CHECK-NEXT: cmp [[RESULT]], w1
; CHECK-NEXT: b.ne [[FAILBB:.?LBB[0-9_]+]] ; CHECK-NEXT: b.ne [[FAILBB:.?LBB[0-9_]+]]
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llvm/trunk/test/CodeGen/AArch64/arm64-big-imm-offsets.ll

; RUN: llc -march=arm64 < %s ; RUN: llc -mtriple=arm64-eabi < %s
; Make sure large offsets aren't mistaken for valid immediate offsets. ; Make sure large offsets aren't mistaken for valid immediate offsets.
; <rdar://problem/13190511> ; <rdar://problem/13190511>
define void @f(i32* nocapture %p) { define void @f(i32* nocapture %p) {
entry: entry:
%a = ptrtoint i32* %p to i64 %a = ptrtoint i32* %p to i64
%ao = add i64 %a, 25769803792 %ao = add i64 %a, 25769803792
%b = inttoptr i64 %ao to i32* %b = inttoptr i64 %ao to i32*
store volatile i32 0, i32* %b, align 4 store volatile i32 0, i32* %b, align 4
store volatile i32 0, i32* %b, align 4 store volatile i32 0, i32* %b, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/arm64-bitfield-extract.ll

; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s ; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
%struct.X = type { i8, i8, [2 x i8] } %struct.X = type { i8, i8, [2 x i8] }
%struct.Y = type { i32, i8 } %struct.Y = type { i32, i8 }
%struct.Z = type { i8, i8, [2 x i8], i16 } %struct.Z = type { i8, i8, [2 x i8], i16 }
%struct.A = type { i64, i8 } %struct.A = type { i64, i8 }
define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp { define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ubfx ; CHECK: ubfx
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llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; Check that building up a vector w/ only one non-zero lane initializes ; Check that building up a vector w/ only one non-zero lane initializes
; intelligently. ; intelligently.
define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind { define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
; CHECK-LABEL: one_lane: ; CHECK-LABEL: one_lane:
; CHECK: dup.16b v[[REG:[0-9]+]], wzr ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
; CHECK-NEXT: ins.b v[[REG]][0], w1 ; CHECK-NEXT: ins.b v[[REG]][0], w1
; v and q are aliases, and str is preferred against st.16b when possible ; v and q are aliases, and str is preferred against st.16b when possible
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llvm/trunk/test/CodeGen/AArch64/arm64-builtins-linux.ll

; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i8* @llvm.thread.pointer() #1 declare i8* @llvm.thread.pointer() #1
define i8* @thread_pointer() { define i8* @thread_pointer() {
; CHECK: thread_pointer: ; CHECK: thread_pointer:
; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
%1 = tail call i8* @llvm.thread.pointer() %1 = tail call i8* @llvm.thread.pointer()
ret i8* %1 ret i8* %1
} }

llvm/trunk/test/CodeGen/AArch64/arm64-cast-opt.ll

; RUN: llc -O3 -march=arm64 -mtriple arm64-apple-ios5.0.0 < %s | FileCheck %s ; RUN: llc -O3 -mtriple arm64-apple-ios5.0.0 < %s | FileCheck %s
; <rdar://problem/15992732> ; <rdar://problem/15992732>
; Zero truncation is not necessary when the values are extended properly ; Zero truncation is not necessary when the values are extended properly
; already. ; already.
@block = common global i8* null, align 8 @block = common global i8* null, align 8
define zeroext i8 @foo(i32 %i1, i32 %i2) { define zeroext i8 @foo(i32 %i1, i32 %i2) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
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llvm/trunk/test/CodeGen/AArch64/arm64-clrsb.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1) #0 declare i32 @llvm.ctlz.i32(i32, i1) #0
declare i64 @llvm.ctlz.i64(i64, i1) #1 declare i64 @llvm.ctlz.i64(i64, i1) #1
; Function Attrs: nounwind ssp ; Function Attrs: nounwind ssp
define i32 @clrsb32(i32 %x) #2 { define i32 @clrsb32(i32 %x) #2 {
entry: entry:
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llvm/trunk/test/CodeGen/AArch64/arm64-coalesce-ext.ll

; RUN: llc -march=arm64 -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Check that the peephole optimizer knows about sext and zext instructions. ; Check that the peephole optimizer knows about sext and zext instructions.
; CHECK: test1sext ; CHECK: test1sext
define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind { define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
%C = add i64 %A, %B %C = add i64 %A, %B
; CHECK: add x[[SUM:[0-9]+]], x0, x1 ; CHECK: add x[[SUM:[0-9]+]], x0, x1
%D = trunc i64 %C to i32 %D = trunc i64 %C to i32
%E = shl i64 %C, 32 %E = shl i64 %C, 32
%F = ashr i64 %E, 32 %F = ashr i64 %E, 32
; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]] ; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]]
store volatile i64 %F, i64 *%P2 store volatile i64 %F, i64 *%P2
; CHECK: str x[[EXT]] ; CHECK: str x[[EXT]]
store volatile i32 %D, i32* %P store volatile i32 %D, i32* %P
; Reuse low bits of extended register, don't extend live range of SUM. ; Reuse low bits of extended register, don't extend live range of SUM.
; CHECK: str w[[SUM]] ; CHECK: str w[[SUM]]
ret i32 %D ret i32 %D
} }

llvm/trunk/test/CodeGen/AArch64/arm64-complex-ret.ll

; RUN: llc -march=arm64 -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi -o - %s | FileCheck %s
define { i192, i192, i21, i192 } @foo(i192) { define { i192, i192, i21, i192 } @foo(i192) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: stp xzr, xzr, [x8] ; CHECK: stp xzr, xzr, [x8]
ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3} ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3}
} }

llvm/trunk/test/CodeGen/AArch64/arm64-convert-v4f64.ll

; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) {
; CHECK: fptosi_v4f64_to_v4i16 ; CHECK: fptosi_v4f64_to_v4i16
; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
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llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll

; RUN: llc -march=arm64 -mattr=+crc -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) { define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b: ; CHECK-LABEL: test_crc32b:
; CHECK: crc32b w0, w0, w1 ; CHECK: crc32b w0, w0, w1
%bits = zext i8 %next to i32 %bits = zext i8 %next to i32
%val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits) %val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits)
ret i32 %val ret i32 %val
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-crypto.ll

; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) { define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: test_aese: ; CHECK-LABEL: test_aese:
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llvm/trunk/test/CodeGen/AArch64/arm64-cvt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; ;
; Floating-point scalar convert to signed integer (to nearest with ties to away) ; Floating-point scalar convert to signed integer (to nearest with ties to away)
; ;
define i32 @fcvtas_1w1s(float %A) nounwind { define i32 @fcvtas_1w1s(float %A) nounwind {
;CHECK-LABEL: fcvtas_1w1s: ;CHECK-LABEL: fcvtas_1w1s:
;CHECK: fcvtas w0, s0 ;CHECK: fcvtas w0, s0
;CHECK-NEXT: ret ;CHECK-NEXT: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-dead-def-frame-index.ll

; RUN: llc -march=arm64 < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define i32 @test1() #0 { define i32 @test1() #0 {
%tmp1 = alloca i8 %tmp1 = alloca i8
%tmp2 = alloca i32, i32 4096 %tmp2 = alloca i32, i32 4096
%tmp3 = icmp eq i8* %tmp1, null %tmp3 = icmp eq i8* %tmp1, null
%tmp4 = zext i1 %tmp3 to i32 %tmp4 = zext i1 %tmp3 to i32
ret i32 %tmp4 ret i32 %tmp4
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12 ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12
; CHECK: adds [[TEMP]], [[TEMP]], #15 ; CHECK: adds [[TEMP]], [[TEMP]], #15
} }

llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind { define <8 x i8> @v_dup8(i8 %A) nounwind {
;CHECK-LABEL: v_dup8: ;CHECK-LABEL: v_dup8:
;CHECK: dup.8b ;CHECK: dup.8b
%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0 %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1 %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2 %tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
%tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3 %tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
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llvm/trunk/test/CodeGen/AArch64/arm64-ext.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: test_vextd: ;CHECK-LABEL: test_vextd:
;CHECK: {{ext.8b.*#3}} ;CHECK: {{ext.8b.*#3}}
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-extend-int-to-fp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <4 x float> @foo(<4 x i16> %a) nounwind { define <4 x float> @foo(<4 x i16> %a) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ushll.4s v0, v0, #0 ; CHECK: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0 ; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vcvt.i = uitofp <4 x i16> %a to <4 x float> %vcvt.i = uitofp <4 x i16> %a to <4 x float>
ret <4 x float> %vcvt.i ret <4 x float> %vcvt.i
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llvm/trunk/test/CodeGen/AArch64/arm64-extload-knownzero.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; rdar://12771555 ; rdar://12771555
define void @foo(i16* %ptr, i32 %a) nounwind { define void @foo(i16* %ptr, i32 %a) nounwind {
entry: entry:
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100 %tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2 br i1 %tmp1, label %bb1, label %bb2
bb1: bb1:
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llvm/trunk/test/CodeGen/AArch64/arm64-extract.ll

; RUN: llc -verify-machineinstrs < %s \ ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
; RUN: -march=arm64 | FileCheck %s
define i64 @ror_i64(i64 %in) { define i64 @ror_i64(i64 %in) {
; CHECK-LABEL: ror_i64: ; CHECK-LABEL: ror_i64:
%left = shl i64 %in, 19 %left = shl i64 %in, 19
%right = lshr i64 %in, 45 %right = lshr i64 %in, 45
%val5 = or i64 %left, %right %val5 = or i64 %left, %right
; CHECK: ror {{x[0-9]+}}, x0, #45 ; CHECK: ror {{x[0-9]+}}, x0, #45
ret i64 %val5 ret i64 %val5
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llvm/trunk/test/CodeGen/AArch64/arm64-extract_subvector.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn. ; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
define <8 x i8> @v8i8(<16 x i8> %a) nounwind { define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
; CHECK: v8i8 ; CHECK: v8i8
; CHECK: ext.16b v0, v0, v0, #8 ; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret ; CHECK: ret
%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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llvm/trunk/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define void @caller(i32* nocapture %p, i32 %a, i32 %b) nounwind optsize ssp { define void @caller(i32* nocapture %p, i32 %a, i32 %b) nounwind optsize ssp {
; CHECK-NOT: stp ; CHECK-NOT: stp
; CHECK: b {{_callee|callee}} ; CHECK: b {{_callee|callee}}
; CHECK-NOT: ldp ; CHECK-NOT: ldp
; CHECK: ret ; CHECK: ret
%1 = icmp eq i32 %b, 0 %1 = icmp eq i32 %b, 0
br i1 %1, label %3, label %2 br i1 %1, label %3, label %2
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llvm/trunk/test/CodeGen/AArch64/arm64-fcmp-opt.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
; rdar://10263824 ; rdar://10263824
define i1 @fcmp_float1(float %a) nounwind ssp { define i1 @fcmp_float1(float %a) nounwind ssp {
entry: entry:
; CHECK-LABEL: @fcmp_float1 ; CHECK-LABEL: @fcmp_float1
; CHECK: fcmp s0, #0.0 ; CHECK: fcmp s0, #0.0
; CHECK: cset w0, ne ; CHECK: cset w0, ne
%cmp = fcmp une float %a, 0.000000e+00 %cmp = fcmp une float %a, 0.000000e+00
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llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; DAGCombine to transform a conversion of an extract_vector_elt to an ; DAGCombine to transform a conversion of an extract_vector_elt to an
; extract_vector_elt of a conversion, which saves a round trip of copies ; extract_vector_elt of a conversion, which saves a round trip of copies
; of the value to a GPR and back to and FPR. ; of the value to a GPR and back to and FPR.
; rdar://11855286 ; rdar://11855286
define double @foo0(<2 x i64> %a) nounwind { define double @foo0(<2 x i64> %a) nounwind {
; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9 ; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
; CHECK-NEXT: mov d0, [[REG]][1] ; CHECK-NEXT: mov d0, [[REG]][1]
%vecext = extractelement <2 x i64> %a, i32 1 %vecext = extractelement <2 x i64> %a, i32 1
%fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9) %fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
ret double %fcvt_n ret double %fcvt_n
} }
declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/arm64-fmadd.ll

; RUN: llc -march=arm64 < %s | FileCheck %s ; RUN: llc -mtriple=arm64-eabi < %s | FileCheck %s
define float @fma32(float %a, float %b, float %c) nounwind readnone ssp { define float @fma32(float %a, float %b, float %c) nounwind readnone ssp {
entry: entry:
; CHECK-LABEL: fma32: ; CHECK-LABEL: fma32:
; CHECK: fmadd s0, s0, s1, s2 ; CHECK: fmadd s0, s0, s1, s2
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %0 ret float %0
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-fmax-safe.ll

; RUN: llc -march=arm64 < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define double @test_direct(float %in) { define double @test_direct(float %in) {
; CHECK-LABEL: test_direct: ; CHECK-LABEL: test_direct:
%cmp = fcmp olt float %in, 0.000000e+00 %cmp = fcmp olt float %in, 0.000000e+00
%val = select i1 %cmp, float 0.000000e+00, float %in %val = select i1 %cmp, float 0.000000e+00, float %in
%longer = fpext float %val to double %longer = fpext float %val to double
ret double %longer ret double %longer
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llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll

; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -enable-no-nans-fp-math | FileCheck %s
define double @test_direct(float %in) { define double @test_direct(float %in) {
; CHECK-LABEL: test_direct: ; CHECK-LABEL: test_direct:
%cmp = fcmp nnan olt float %in, 0.000000e+00 %cmp = fcmp nnan olt float %in, 0.000000e+00
%val = select i1 %cmp, float 0.000000e+00, float %in %val = select i1 %cmp, float 0.000000e+00, float %in
%longer = fpext float %val to double %longer = fpext float %val to double
ret double %longer ret double %longer
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llvm/trunk/test/CodeGen/AArch64/arm64-fmuladd.ll

; RUN: llc -asm-verbose=false < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -asm-verbose=false -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define float @test_f32(float* %A, float* %B, float* %C) nounwind { define float @test_f32(float* %A, float* %B, float* %C) nounwind {
;CHECK-LABEL: test_f32: ;CHECK-LABEL: test_f32:
;CHECK: fmadd ;CHECK: fmadd
;CHECK-NOT: fmadd ;CHECK-NOT: fmadd
%tmp1 = load float, float* %A %tmp1 = load float, float* %A
%tmp2 = load float, float* %B %tmp2 = load float, float* %B
%tmp3 = load float, float* %C %tmp3 = load float, float* %C
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llvm/trunk/test/CodeGen/AArch64/arm64-fold-lsl.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; ;
; <rdar://problem/14486451> ; <rdar://problem/14486451>
%struct.a = type [256 x i16] %struct.a = type [256 x i16]
%struct.b = type [256 x i32] %struct.b = type [256 x i32]
%struct.c = type [256 x i64] %struct.c = type [256 x i64]
define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind { define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind {
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llvm/trunk/test/CodeGen/AArch64/arm64-fp.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define float @t1(i1 %a, float %b, float %c) nounwind { define float @t1(i1 %a, float %b, float %c) nounwind {
; CHECK: t1 ; CHECK: t1
; CHECK: fcsel s0, s0, s1, ne ; CHECK: fcsel s0, s0, s1, ne
%sel = select i1 %a, float %b, float %c %sel = select i1 %a, float %b, float %c
ret float %sel ret float %sel
} }

llvm/trunk/test/CodeGen/AArch64/arm64-fp128-folding.ll

; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
declare void @bar(i8*, i8*, i32*) declare void @bar(i8*, i8*, i32*)
; SelectionDAG used to try to fold some fp128 operations using the ppc128 type, ; SelectionDAG used to try to fold some fp128 operations using the ppc128 type,
; which is not supported. ; which is not supported.
define fp128 @test_folding() { define fp128 @test_folding() {
; CHECK-LABEL: test_folding: ; CHECK-LABEL: test_folding:
%l = alloca i32 %l = alloca i32
store i32 42, i32* %l store i32 42, i32* %l
%val = load i32, i32* %l %val = load i32, i32* %l
%fpval = sitofp i32 %val to fp128 %fpval = sitofp i32 %val to fp128
; If the value is loaded from a constant pool into an fp128, it's been folded ; If the value is loaded from a constant pool into an fp128, it's been folded
; successfully. ; successfully.
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}},
ret fp128 %fpval ret fp128 %fpval
} }

llvm/trunk/test/CodeGen/AArch64/arm64-frame-index.ll

; RUN: llc -march=arm64 -mtriple=arm64-apple-ios -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-atomic-cfg-tidy=0 | FileCheck %s
; rdar://11935841 ; rdar://11935841
define void @t1() nounwind ssp { define void @t1() nounwind ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK-NOT: add x{{[0-9]+}}, sp ; CHECK-NOT: add x{{[0-9]+}}, sp
; CHECK: stp x28, x27, [sp, #-16]! ; CHECK: stp x28, x27, [sp, #-16]!
%v = alloca [288 x i32], align 4 %v = alloca [288 x i32], align 4
unreachable unreachable
} }

llvm/trunk/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define i32 @foo(<4 x i16>* %__a) nounwind { define i32 @foo(<4 x i16>* %__a) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: umov.h w{{[0-9]+}}, v{{[0-9]+}}[0] ; CHECK: umov.h w{{[0-9]+}}, v{{[0-9]+}}[0]
%tmp18 = load <4 x i16>, <4 x i16>* %__a, align 8 %tmp18 = load <4 x i16>, <4 x i16>* %__a, align 8
%vget_lane = extractelement <4 x i16> %tmp18, i32 0 %vget_lane = extractelement <4 x i16> %tmp18, i32 0
%conv = zext i16 %vget_lane to i32 %conv = zext i16 %vget_lane to i32
%mul = mul nsw i32 3, %conv %mul = mul nsw i32 3, %conv
ret i32 %mul ret i32 %mul
} }

llvm/trunk/test/CodeGen/AArch64/arm64-icmp-opt.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; Optimize (x > -1) to (x >= 0) etc. ; Optimize (x > -1) to (x >= 0) etc.
; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag ; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
; for comparison only ; for comparison only
; rdar://10233472 ; rdar://10233472
define i32 @t1(i64 %a) nounwind ssp { define i32 @t1(i64 %a) nounwind ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK-NOT: movn ; CHECK-NOT: movn
; CHECK: cmp x0, #0 ; CHECK: cmp x0, #0
; CHECK: cset w0, ge ; CHECK: cset w0, ge
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }

llvm/trunk/test/CodeGen/AArch64/arm64-indexed-memory.ll

; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s
define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind noinline ssp { define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind noinline ssp {
; CHECK-LABEL: store64: ; CHECK-LABEL: store64:
; CHECK: str x{{[0-9+]}}, [x{{[0-9+]}}], #8 ; CHECK: str x{{[0-9+]}}, [x{{[0-9+]}}], #8
; CHECK: ret ; CHECK: ret
%tmp = load i64*, i64** %out, align 8 %tmp = load i64*, i64** %out, align 8
%incdec.ptr = getelementptr inbounds i64, i64* %tmp, i64 1 %incdec.ptr = getelementptr inbounds i64, i64* %tmp, i64 1
store i64 %spacing, i64* %tmp, align 4 store i64 %spacing, i64* %tmp, align 4
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llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'I' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
define i32 @constraint_I(i32 %i, i32 %j) nounwind ssp { define i32 @constraint_I(i32 %i, i32 %j) nounwind ssp {
entry: entry:
%0 = tail call i32 asm sideeffect "add $0, $1, $2", "=r,r,I"(i32 %i, i32 4097) nounwind %0 = tail call i32 asm sideeffect "add $0, $1, $2", "=r,r,I"(i32 %i, i32 4097) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'J' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
define i32 @constraint_J(i32 %i, i32 %j) nounwind ssp { define i32 @constraint_J(i32 %i, i32 %j) nounwind ssp {
entry: entry:
%0 = tail call i32 asm sideeffect "sub $0, $1, $2", "=r,r,J"(i32 %i, i32 2) nounwind %0 = tail call i32 asm sideeffect "sub $0, $1, $2", "=r,r,J"(i32 %i, i32 2) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'K' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
define i32 @constraint_K(i32 %i, i32 %j) nounwind { define i32 @constraint_K(i32 %i, i32 %j) nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,K"(i32 %i, i32 -1) nounwind %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,K"(i32 %i, i32 -1) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'L' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
define i32 @constraint_L(i32 %i, i32 %j) nounwind { define i32 @constraint_L(i32 %i, i32 %j) nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,L"(i32 %i, i64 -1) nounwind %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,L"(i32 %i, i64 -1) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'M' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'M'
define i32 @constraint_M(i32 %i, i32 %j) nounwind { define i32 @constraint_M(i32 %i, i32 %j) nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "movk $0, $1", "=r,M"(i32 305418240) nounwind %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,M"(i32 305418240) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll

; RUN: not llc -march=arm64 < %s 2> %t ; RUN: not llc -mtriple=arm64-eabi < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant. ; Check for at least one invalid constant.
; CHECK-ERRORS: error: invalid operand for inline asm constraint 'N' ; CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
define i32 @constraint_N(i32 %i, i32 %j) nounwind { define i32 @constraint_N(i32 %i, i32 %j) nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "movk $0, $1", "=r,N"(i64 1311761352401879040) nounwind %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,N"(i64 1311761352401879040) nounwind
ret i32 %0 ret i32 %0
} }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-zero-reg-error.ll

; RUN: not llc < %s -march=arm64 2>&1 | FileCheck %s ; RUN: not llc < %s -mtriple=arm64-eabi 2>&1 | FileCheck %s
; The 'z' constraint allocates either xzr or wzr, but obviously an input of 1 is ; The 'z' constraint allocates either xzr or wzr, but obviously an input of 1 is
; incompatible. ; incompatible.
define void @test_bad_zero_reg() { define void @test_bad_zero_reg() {
tail call void asm sideeffect "USE($0)", "z"(i32 1) nounwind tail call void asm sideeffect "USE($0)", "z"(i32 1) nounwind
; CHECK: error: invalid operand for inline asm constraint 'z' ; CHECK: error: invalid operand for inline asm constraint 'z'
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/arm64-ld1.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind { define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind {
; CHECK-LABEL: ld2_8b ; CHECK-LABEL: ld2_8b
; Make sure we are loading into the results defined by the ABI (i.e., v0, v1) ; Make sure we are loading into the results defined by the ABI (i.e., v0, v1)
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llvm/trunk/test/CodeGen/AArch64/arm64-ldp-aa.ll

; RUN: llc < %s -march=arm64 -enable-misched=false -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -enable-misched=false -verify-machineinstrs | FileCheck %s
; The next set of tests makes sure we can combine the second instruction into ; The next set of tests makes sure we can combine the second instruction into
; the first. ; the first.
; CHECK-LABEL: ldp_int_aa ; CHECK-LABEL: ldp_int_aa
; CHECK: ldp w8, w9, [x1] ; CHECK: ldp w8, w9, [x1]
; CHECK: str w0, [x1, #8] ; CHECK: str w0, [x1, #8]
; CHECK: ret ; CHECK: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-ldp.ll

; RUN: llc < %s -march=arm64 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: ldp_int ; CHECK-LABEL: ldp_int
; CHECK: ldp ; CHECK: ldp
define i32 @ldp_int(i32* %p) nounwind { define i32 @ldp_int(i32* %p) nounwind {
%tmp = load i32, i32* %p, align 4 %tmp = load i32, i32* %p, align 4
%add.ptr = getelementptr inbounds i32, i32* %p, i64 1 %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
%tmp1 = load i32, i32* %add.ptr, align 4 %tmp1 = load i32, i32* %add.ptr, align 4
%add = add nsw i32 %tmp1, %tmp %add = add nsw i32 %tmp1, %tmp
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llvm/trunk/test/CodeGen/AArch64/arm64-ldur.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define i64 @_f0(i64* %p) { define i64 @_f0(i64* %p) {
; CHECK: f0: ; CHECK: f0:
; CHECK: ldur x0, [x0, #-8] ; CHECK: ldur x0, [x0, #-8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = getelementptr inbounds i64, i64* %p, i64 -1 %tmp = getelementptr inbounds i64, i64* %p, i64 -1
%ret = load i64, i64* %tmp, align 2 %ret = load i64, i64* %tmp, align 2
ret i64 %ret ret i64 %ret
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llvm/trunk/test/CodeGen/AArch64/arm64-leaf.ll

; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
; rdar://12829704 ; rdar://12829704
define void @t8() nounwind ssp { define void @t8() nounwind ssp {
; CHECK-LABEL: t8: ; CHECK-LABEL: t8:
; CHECK-NOT: stp fp, lr, [sp, #-16]! ; CHECK-NOT: stp fp, lr, [sp, #-16]!
; CHECK-NOT: mov fp, sp ; CHECK-NOT: mov fp, sp
; CHECK: nop ; CHECK: nop
; CHECK-NOT: mov sp, fp ; CHECK-NOT: mov sp, fp
; CHECK-NOT: ldp fp, lr, [sp], #16 ; CHECK-NOT: ldp fp, lr, [sp], #16
tail call void asm sideeffect "nop", "~{v8}"() nounwind tail call void asm sideeffect "nop", "~{v8}"() nounwind
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/arm64-long-shift.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
define i128 @shl(i128 %r, i128 %s) nounwind readnone { define i128 @shl(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: shl: ; CHECK-LABEL: shl:
; CHECK: orr w[[SIXTY_FOUR:[0-9]+]], wzr, #0x40 ; CHECK: orr w[[SIXTY_FOUR:[0-9]+]], wzr, #0x40
; CHECK: sub [[REV_SHIFT:x[0-9]+]], x[[SIXTY_FOUR]], x2 ; CHECK: sub [[REV_SHIFT:x[0-9]+]], x[[SIXTY_FOUR]], x2
; CHECK: lsr [[LO_FOR_HI_NORMAL:x[0-9]+]], x0, [[REV_SHIFT]] ; CHECK: lsr [[LO_FOR_HI_NORMAL:x[0-9]+]], x0, [[REV_SHIFT]]
; CHECK: cmp x2, #0 ; CHECK: cmp x2, #0
; CHECK: csel [[LO_FOR_HI:x[0-9]+]], xzr, [[LO_FOR_HI_NORMAL]], eq ; CHECK: csel [[LO_FOR_HI:x[0-9]+]], xzr, [[LO_FOR_HI_NORMAL]], eq
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llvm/trunk/test/CodeGen/AArch64/arm64-memcpy-inline.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
@src = external global %struct.x @src = external global %struct.x
@dst = external global %struct.x @dst = external global %struct.x
@.str1 = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 1 @.str1 = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 1
@.str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1 @.str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1
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llvm/trunk/test/CodeGen/AArch64/arm64-memset-inline.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define void @t1(i8* nocapture %c) nounwind optsize { define void @t1(i8* nocapture %c) nounwind optsize {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: str wzr, [x0, #8] ; CHECK: str wzr, [x0, #8]
; CHECK: str xzr, [x0] ; CHECK: str xzr, [x0]
call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false) call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
ret void ret void
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llvm/trunk/test/CodeGen/AArch64/arm64-movi.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
;==--------------------------------------------------------------------------== ;==--------------------------------------------------------------------------==
; Tests for MOV-immediate implemented with ORR-immediate. ; Tests for MOV-immediate implemented with ORR-immediate.
;==--------------------------------------------------------------------------== ;==--------------------------------------------------------------------------==
; 64-bit immed with 32-bit pattern size, rotated by 0. ; 64-bit immed with 32-bit pattern size, rotated by 0.
define i64 @test64_32_rot0() nounwind { define i64 @test64_32_rot0() nounwind {
; CHECK-LABEL: test64_32_rot0: ; CHECK-LABEL: test64_32_rot0:
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llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; rdar://9296808 ; rdar://9296808
; rdar://9349137 ; rdar://9349137
define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp { define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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llvm/trunk/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a
; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple
declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>) declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32) declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32)
declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16) declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16)
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llvm/trunk/test/CodeGen/AArch64/arm64-popcnt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -march=aarch64 -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s ; RUN: llc < %s -mtriple=aarch64-eabi -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
define i32 @cnt32_advsimd(i32 %x) nounwind readnone { define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x) %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt ret i32 %cnt
; CHECK: mov w[[IN64:[0-9]+]], w0 ; CHECK: mov w[[IN64:[0-9]+]], w0
; CHECK: fmov d0, x[[IN64]] ; CHECK: fmov d0, x[[IN64]]
; CHECK: cnt.8b v0, v0 ; CHECK: cnt.8b v0, v0
; CHECK: uaddlv.8b h0, v0 ; CHECK: uaddlv.8b h0, v0
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llvm/trunk/test/CodeGen/AArch64/arm64-prefetch.ll

; RUN: llc %s -march arm64 -o - | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
@a = common global i32* null, align 8 @a = common global i32* null, align 8
define void @test(i32 %i, i32 %j) nounwind ssp { define void @test(i32 %i, i32 %j) nounwind ssp {
entry: entry:
; CHECK: @test ; CHECK: @test
%j.addr = alloca i32, align 4 %j.addr = alloca i32, align 4
store i32 %j, i32* %j.addr, align 4, !tbaa !0 store i32 %j, i32* %j.addr, align 4, !tbaa !0
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llvm/trunk/test/CodeGen/AArch64/arm64-redzone.ll

; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s
define i32 @foo(i32 %a, i32 %b) nounwind ssp { define i32 @foo(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK-NOT: sub sp, sp ; CHECK-NOT: sub sp, sp
; CHECK: ret ; CHECK: ret
%a.addr = alloca i32, align 4 %a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4 %b.addr = alloca i32, align 4
%x = alloca i32, align 4 %x = alloca i32, align 4
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llvm/trunk/test/CodeGen/AArch64/arm64-regress-f128csel-flags.ll

; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s
; We used to not mark NZCV as being used in the continuation basic-block ; We used to not mark NZCV as being used in the continuation basic-block
; when lowering a 128-bit "select" to branches. This meant a subsequent use ; when lowering a 128-bit "select" to branches. This meant a subsequent use
; of the same flags gave an internal fault here. ; of the same flags gave an internal fault here.
declare void @foo(fp128) declare void @foo(fp128)
define double @test_f128csel_flags(i32 %lhs, fp128 %a, fp128 %b, double %l, double %r) nounwind { define double @test_f128csel_flags(i32 %lhs, fp128 %a, fp128 %b, double %l, double %r) nounwind {
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llvm/trunk/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll

; RUN: llc -march=arm64 -o - %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; This is mostly a "don't assert" test. The type of the RHS of a shift depended ; This is mostly a "don't assert" test. The type of the RHS of a shift depended
; on the phase of legalization, which led to the creation of an unexpected and ; on the phase of legalization, which led to the creation of an unexpected and
; unselectable "rotr" node: (i32 (rotr i32, i64)). ; unselectable "rotr" node: (i32 (rotr i32, i64)).
; FIXME: This test is xfailed because it relies on an optimization that has ; FIXME: This test is xfailed because it relies on an optimization that has
; been reverted (see PR17975). ; been reverted (see PR17975).
; XFAIL: * ; XFAIL: *
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llvm/trunk/test/CodeGen/AArch64/arm64-return-vector.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; 2x64 vector should be returned in Q0. ; 2x64 vector should be returned in Q0.
define <2 x double> @test(<2 x double>* %p) nounwind { define <2 x double> @test(<2 x double>* %p) nounwind {
; CHECK: test ; CHECK: test
; CHECK: ldr q0, [x0] ; CHECK: ldr q0, [x0]
; CHECK: ret ; CHECK: ret
%tmp1 = load <2 x double>, <2 x double>* %p, align 16 %tmp1 = load <2 x double>, <2 x double>* %p, align 16
ret <2 x double> %tmp1 ret <2 x double> %tmp1
} }

llvm/trunk/test/CodeGen/AArch64/arm64-returnaddr.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define i8* @rt0(i32 %x) nounwind readnone { define i8* @rt0(i32 %x) nounwind readnone {
entry: entry:
; CHECK-LABEL: rt0: ; CHECK-LABEL: rt0:
; CHECK: mov x0, x30 ; CHECK: mov x0, x30
; CHECK: ret ; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 0) %0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0 ret i8* %0
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llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define i32 @test_rev_w(i32 %a) nounwind { define i32 @test_rev_w(i32 %a) nounwind {
entry: entry:
; CHECK-LABEL: test_rev_w: ; CHECK-LABEL: test_rev_w:
; CHECK: rev w0, w0 ; CHECK: rev w0, w0
%0 = tail call i32 @llvm.bswap.i32(i32 %a) %0 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %0 ret i32 %0
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-scvt.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -march=arm64 -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
; rdar://13082402 ; rdar://13082402
define float @t1(i32* nocapture %src) nounwind ssp { define float @t1(i32* nocapture %src) nounwind ssp {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: ldr s0, [x0] ; CHECK: ldr s0, [x0]
; CHECK: scvtf s0, s0 ; CHECK: scvtf s0, s0
%tmp1 = load i32, i32* %src, align 4 %tmp1 = load i32, i32* %src, align 4
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llvm/trunk/test/CodeGen/AArch64/arm64-shifted-sext.ll

; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
; ;
; <rdar://problem/13820218> ; <rdar://problem/13820218>
define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp { define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
entry: entry:
; CHECK-LABEL: extendedLeftShiftcharToshortBy4: ; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
; CHECK: add [[REG:w[0-9]+]], w0, #1 ; CHECK: add [[REG:w[0-9]+]], w0, #1
; CHECK: sbfiz w0, [[REG]], #4, #8 ; CHECK: sbfiz w0, [[REG]], #4, #8
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llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll

; RUN: llc -march=arm64 < %s ; RUN: llc < %s -mtriple=arm64-eabi
; The DAGCombiner tries to do following shrink: ; The DAGCombiner tries to do following shrink:
; Convert x+y to (VT)((SmallVT)x+(SmallVT)y) ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
; But currently it can't handle vector type and will trigger an assertion failure ; But currently it can't handle vector type and will trigger an assertion failure
; when it tries to generate an add mixed using vector type and scaler type. ; when it tries to generate an add mixed using vector type and scaler type.
; This test checks that such assertion failur should not happen. ; This test checks that such assertion failur should not happen.
define <1 x i64> @dotest(<1 x i64> %in0) { define <1 x i64> @dotest(<1 x i64> %in0) {
entry: entry:
%0 = add <1 x i64> %in0, %in0 %0 = add <1 x i64> %in0, %in0
%vshl_n = shl <1 x i64> %0, <i64 32> %vshl_n = shl <1 x i64> %0, <i64 32>
%vsra_n = ashr <1 x i64> %vshl_n, <i64 32> %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
ret <1 x i64> %vsra_n ret <1 x i64> %vsra_n
} }

llvm/trunk/test/CodeGen/AArch64/arm64-simd-scalar-to-vector.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp { define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
; CHECK: uaddlv.16b h0, v0 ; CHECK: uaddlv.16b h0, v0
; CHECK: rshrn.8b v0, v0, #4 ; CHECK: rshrn.8b v0, v0, #4
; CHECK: dup.16b v0, v0[0] ; CHECK: dup.16b v0, v0[0]
; CHECK: ret ; CHECK: ret
; CHECK-FAST: uaddlv.16b ; CHECK-FAST: uaddlv.16b
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llvm/trunk/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll

; RUN: llc -march=arm64 -o - %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency ; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency
; but not updating chain-successors of the old one. As a result, the two memory ; but not updating chain-successors of the old one. As a result, the two memory
; operations in this function both ended up direct successors to the EntryToken ; operations in this function both ended up direct successors to the EntryToken
; and could be reordered. ; and could be reordered.
@var = global i32 0, align 4 @var = global i32 0, align 4
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llvm/trunk/test/CodeGen/AArch64/arm64-sli-sri-opt.ll

; RUN: llc -aarch64-shift-insert-generation=true -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -aarch64-shift-insert-generation=true -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind { define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
; CHECK-LABEL: testLeftGood: ; CHECK-LABEL: testLeftGood:
; CHECK: sli.16b v0, v1, #3 ; CHECK: sli.16b v0, v1, #3
%and.i = and <16 x i8> %src1, <i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252> %and.i = and <16 x i8> %src1, <i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252>
%vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%result = or <16 x i8> %and.i, %vshl_n %result = or <16 x i8> %and.i, %vshl_n
store <16 x i8> %result, <16 x i8>* %dest, align 16 store <16 x i8> %result, <16 x i8>* %dest, align 16
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llvm/trunk/test/CodeGen/AArch64/arm64-smaxv.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vmaxv_s8(<8 x i8> %a1) { define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
; CHECK: test_vmaxv_s8 ; CHECK: test_vmaxv_s8
; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
; CHECK-NEXT: smov.b w0, v[[REGNUM]][0] ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1) %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
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llvm/trunk/test/CodeGen/AArch64/arm64-sminv.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vminv_s8(<8 x i8> %a1) { define signext i8 @test_vminv_s8(<8 x i8> %a1) {
; CHECK: test_vminv_s8 ; CHECK: test_vminv_s8
; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
; CHECK-NEXT: smov.b w0, v[[REGNUM]][0] ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1) %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
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llvm/trunk/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll

; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi | FileCheck %s
; Check if sqshl/uqshl with constant shift amout can be selected. ; Check if sqshl/uqshl with constant shift amout can be selected.
define i64 @test_vqshld_s64_i(i64 %a) { define i64 @test_vqshld_s64_i(i64 %a) {
; CHECK-LABEL: test_vqshld_s64_i: ; CHECK-LABEL: test_vqshld_s64_i:
; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36 ; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
%1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36) %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
ret i64 %1 ret i64 %1
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-st1.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
define void @st1lane_16b(<16 x i8> %A, i8* %D) { define void @st1lane_16b(<16 x i8> %A, i8* %D) {
; CHECK-LABEL: st1lane_16b ; CHECK-LABEL: st1lane_16b
; CHECK: st1.b ; CHECK: st1.b
%tmp = extractelement <16 x i8> %A, i32 1 %tmp = extractelement <16 x i8> %A, i32 1
store i8 %tmp, i8* %D store i8 %tmp, i8* %D
ret void ret void
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll

; RUN: llc < %s -march=arm64 -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -enable-misched=false -aarch64-stp-suppress=false -verify-machineinstrs | FileCheck %s
; The next set of tests makes sure we can combine the second instruction into ; The next set of tests makes sure we can combine the second instruction into
; the first. ; the first.
; CHECK-LABEL: stp_int_aa ; CHECK-LABEL: stp_int_aa
; CHECK: stp w0, w1, [x2] ; CHECK: stp w0, w1, [x2]
; CHECK: ldr w0, [x2, #8] ; CHECK: ldr w0, [x2, #8]
; CHECK: ret ; CHECK: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-stp.ll

; RUN: llc < %s -march=arm64 -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
; CHECK-LABEL: stp_int ; CHECK-LABEL: stp_int
; CHECK: stp w0, w1, [x2] ; CHECK: stp w0, w1, [x2]
define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind { define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
store i32 %a, i32* %p, align 4 store i32 %a, i32* %p, align 4
%add.ptr = getelementptr inbounds i32, i32* %p, i64 1 %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
store i32 %b, i32* %add.ptr, align 4 store i32 %b, i32* %add.ptr, align 4
ret void ret void
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llvm/trunk/test/CodeGen/AArch64/arm64-stur.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
%struct.X = type <{ i32, i64, i64 }> %struct.X = type <{ i32, i64, i64 }>
define void @foo1(i32* %p, i64 %val) nounwind { define void @foo1(i32* %p, i64 %val) nounwind {
; CHECK-LABEL: foo1: ; CHECK-LABEL: foo1:
; CHECK: stur w1, [x0, #-4] ; CHECK: stur w1, [x0, #-4]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = trunc i64 %val to i32 %tmp1 = trunc i64 %val to i32
%ptr = getelementptr inbounds i32, i32* %p, i64 -1 %ptr = getelementptr inbounds i32, i32* %p, i64 -1
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llvm/trunk/test/CodeGen/AArch64/arm64-subvector-extend.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; Test efficient codegen of vector extends up from legal type to 128 bit ; Test efficient codegen of vector extends up from legal type to 128 bit
; and 256 bit vector types. ; and 256 bit vector types.
;----- ;-----
; Vectors of i16. ; Vectors of i16.
;----- ;-----
define <8 x i16> @func1(<8 x i8> %v0) nounwind { define <8 x i16> @func1(<8 x i8> %v0) nounwind {
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llvm/trunk/test/CodeGen/AArch64/arm64-tbl.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @tbl1_8b(<16 x i8> %A, <8 x i8> %B) nounwind { define <8 x i8> @tbl1_8b(<16 x i8> %A, <8 x i8> %B) nounwind {
; CHECK: tbl1_8b ; CHECK: tbl1_8b
; CHECK: tbl.8b ; CHECK: tbl.8b
%tmp3 = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %A, <8 x i8> %B) %tmp3 = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %A, <8 x i8> %B)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-this-return.ll

; RUN: llc < %s -march=arm64 -aarch64-this-return-forwarding | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-this-return-forwarding | FileCheck %s
%struct.A = type { i8 } %struct.A = type { i8 }
%struct.B = type { i32 } %struct.B = type { i32 }
%struct.C = type { %struct.B } %struct.C = type { %struct.B }
%struct.D = type { %struct.B } %struct.D = type { %struct.B }
%struct.E = type { %struct.B, %struct.B } %struct.E = type { %struct.B, %struct.B }
declare %struct.A* @A_ctor_base(%struct.A* returned) declare %struct.A* @A_ctor_base(%struct.A* returned)
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llvm/trunk/test/CodeGen/AArch64/arm64-trap.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define void @foo() nounwind { define void @foo() nounwind {
; CHECK: foo ; CHECK: foo
; CHECK: brk #0x1 ; CHECK: brk #0x1
tail call void @llvm.trap() tail call void @llvm.trap()
ret void ret void
} }
declare void @llvm.trap() nounwind declare void @llvm.trap() nounwind

llvm/trunk/test/CodeGen/AArch64/arm64-trn.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vtrni8: ;CHECK-LABEL: vtrni8:
;CHECK: trn1.8b ;CHECK: trn1.8b
;CHECK: trn2.8b ;CHECK: trn2.8b
;CHECK-NEXT: add.8b ;CHECK-NEXT: add.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
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llvm/trunk/test/CodeGen/AArch64/arm64-umaxv.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp { define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
; CHECK-LABEL: vmax_u8x8: ; CHECK-LABEL: vmax_u8x8:
; CHECK: umaxv.8b b[[REG:[0-9]+]], v0 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]] ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
; CHECK-NOT: and ; CHECK-NOT: and
; CHECK: cbz [[REG2]], ; CHECK: cbz [[REG2]],
entry: entry:
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llvm/trunk/test/CodeGen/AArch64/arm64-uminv.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp { define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
; CHECK-LABEL: vmin_u8x8: ; CHECK-LABEL: vmin_u8x8:
; CHECK: uminv.8b b[[REG:[0-9]+]], v0 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0
; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]] ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
; CHECK-NOT: and ; CHECK-NOT: and
; CHECK: cbz [[REG2]], ; CHECK: cbz [[REG2]],
entry: entry:
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llvm/trunk/test/CodeGen/AArch64/arm64-umov.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define zeroext i8 @f1(<16 x i8> %a) { define zeroext i8 @f1(<16 x i8> %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: mov.b w0, v0[3] ; CHECK: mov.b w0, v0[3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vecext = extractelement <16 x i8> %a, i32 3 %vecext = extractelement <16 x i8> %a, i32 3
ret i8 %vecext ret i8 %vecext
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-unaligned_ldst.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; rdar://r11231896 ; rdar://r11231896
define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind { define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK-NOT: orr ; CHECK-NOT: orr
; CHECK: ldr [[X0:x[0-9]+]], [x1] ; CHECK: ldr [[X0:x[0-9]+]], [x1]
; CHECK: str [[X0]], [x0] ; CHECK: str [[X0]], [x0]
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llvm/trunk/test/CodeGen/AArch64/arm64-uzp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vuzpi8: ;CHECK-LABEL: vuzpi8:
;CHECK: uzp1.8b ;CHECK: uzp1.8b
;CHECK: uzp2.8b ;CHECK: uzp2.8b
;CHECK-NEXT: add.8b ;CHECK-NEXT: add.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
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llvm/trunk/test/CodeGen/AArch64/arm64-vaargs.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-darwin11.0.0 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
target triple = "arm64-apple-darwin11.0.0"
define float @t1(i8* nocapture %fmt, ...) nounwind ssp { define float @t1(i8* nocapture %fmt, ...) nounwind ssp {
entry: entry:
; CHECK: t1 ; CHECK: t1
; CHECK: fcvt ; CHECK: fcvt
%argp = alloca i8*, align 8 %argp = alloca i8*, align 8
%argp1 = bitcast i8** %argp to i8* %argp1 = bitcast i8** %argp to i8*
call void @llvm.va_start(i8* %argp1) call void @llvm.va_start(i8* %argp1)
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llvm/trunk/test/CodeGen/AArch64/arm64-vabs.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sabdl8h: ;CHECK-LABEL: sabdl8h:
;CHECK: sabdl.8h ;CHECK: sabdl.8h
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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llvm/trunk/test/CodeGen/AArch64/arm64-vadd.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
;CHECK-LABEL: addhn8b: ;CHECK-LABEL: addhn8b:
;CHECK: addhn.8b ;CHECK: addhn.8b
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vaddlv.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone { define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone {
; CHECK: test_vaddlv_s32 ; CHECK: test_vaddlv_s32
; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]] ; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind %vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
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llvm/trunk/test/CodeGen/AArch64/arm64-vaddv.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -asm-verbose=false -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -mcpu=cyclone | FileCheck %s
define signext i8 @test_vaddv_s8(<8 x i8> %a1) { define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
; CHECK-LABEL: test_vaddv_s8: ; CHECK-LABEL: test_vaddv_s8:
; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
; CHECK-NEXT: smov.b w0, v[[REGNUM]][0] ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1) %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)
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llvm/trunk/test/CodeGen/AArch64/arm64-vbitwise.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind { define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
;CHECK-LABEL: rbit_8b: ;CHECK-LABEL: rbit_8b:
;CHECK: rbit.8b ;CHECK: rbit.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1) %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp { define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_u8: ; CHECK-LABEL: test_vclz_u8:
; CHECK: clz.8b v0, v0 ; CHECK: clz.8b v0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
ret <8 x i8> %vclz.i ret <8 x i8> %vclz.i
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vcmp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind { define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind {
;CHECK-LABEL: fcmltz_4s: ;CHECK-LABEL: fcmltz_4s:
;CHECK: fcmlt.4s [[REG:v[0-9]+]], v0, #0 ;CHECK: fcmlt.4s [[REG:v[0-9]+]], v0, #0
;CHECK-NEXT: xtn.4h v[[REG_1:[0-9]+]], [[REG]] ;CHECK-NEXT: xtn.4h v[[REG_1:[0-9]+]], [[REG]]
;CHECK-NEXT: str d[[REG_1]], [x0] ;CHECK-NEXT: str d[[REG_1]], [x0]
;CHECK-NEXT: ret ;CHECK-NEXT: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-vcnt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind { define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
;CHECK-LABEL: cls_8b: ;CHECK-LABEL: cls_8b:
;CHECK: cls.8b ;CHECK: cls.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %tmp1) %tmp3 = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vcombine.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; LowerCONCAT_VECTORS() was reversing the order of two parts. ; LowerCONCAT_VECTORS() was reversing the order of two parts.
; rdar://11558157 ; rdar://11558157
; rdar://11559553 ; rdar://11559553
define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind { define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
entry: entry:
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ins.d v0[1], v1[0] ; CHECK: ins.d v0[1], v1[0]
%0 = bitcast <16 x i8> %q0 to <2 x i64> %0 = bitcast <16 x i8> %q0 to <2 x i64>
%shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
%1 = bitcast <16 x i8> %q1 to <2 x i64> %1 = bitcast <16 x i8> %q1 to <2 x i64>
%shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
%shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1> %shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1>
%2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8> %2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8>
ret <16 x i8> %2 ret <16 x i8> %2
} }

llvm/trunk/test/CodeGen/AArch64/arm64-vcvt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind { define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind {
;CHECK-LABEL: fcvtas_2s: ;CHECK-LABEL: fcvtas_2s:
;CHECK-NOT: ld1 ;CHECK-NOT: ld1
;CHECK: fcvtas.2s v0, v0 ;CHECK: fcvtas.2s v0, v0
;CHECK-NEXT: ret ;CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A) %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3 ret <2 x i32> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -O0 -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp { define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
; CHECK-LABEL: test_vcvt_f64_f32: ; CHECK-LABEL: test_vcvt_f64_f32:
%vcvt1.i = fpext <2 x float> %x to <2 x double> %vcvt1.i = fpext <2 x float> %x to <2 x double>
; CHECK: fcvtl v0.2d, v0.2s ; CHECK: fcvtl v0.2d, v0.2s
ret <2 x double> %vcvt1.i ret <2 x double> %vcvt1.i
; CHECK: ret ; CHECK: ret
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f32_su32.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp { define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: ucvt: ; CHECK-LABEL: ucvt:
; CHECK: ucvtf.2s v0, v0 ; CHECK: ucvtf.2s v0, v0
; CHECK: ret ; CHECK: ret
%vcvt.i = uitofp <2 x i32> %a to <2 x float> %vcvt.i = uitofp <2 x i32> %a to <2 x float>
ret <2 x float> %vcvt.i ret <2 x float> %vcvt.i
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llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_n.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp { define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: cvtf32fxpu: ; CHECK-LABEL: cvtf32fxpu:
; CHECK: ucvtf.2s v0, v0, #9 ; CHECK: ucvtf.2s v0, v0, #9
; CHECK: ret ; CHECK: ret
%vcvt_n1 = tail call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %a, i32 9) %vcvt_n1 = tail call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %a, i32 9)
ret <2 x float> %vcvt_n1 ret <2 x float> %vcvt_n1
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_su32_f32.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp { define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp {
; CHECK: c1 ; CHECK: c1
; CHECK: fcvtzs.2s v0, v0 ; CHECK: fcvtzs.2s v0, v0
; CHECK: ret ; CHECK: ret
%vcvt.i = fptosi <2 x float> %a to <2 x i32> %vcvt.i = fptosi <2 x float> %a to <2 x i32>
ret <2 x i32> %vcvt.i ret <2 x i32> %vcvt.i
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define float @fcvtxn(double %a) { define float @fcvtxn(double %a) {
; CHECK-LABEL: fcvtxn: ; CHECK-LABEL: fcvtxn:
; CHECK: fcvtxn s0, d0 ; CHECK: fcvtxn s0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
ret float %vcvtxd.i ret float %vcvtxd.i
} }
declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/arm64-vecCmpBr.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
; ModuleID = 'arm64_vecCmpBr.c' ; ModuleID = 'arm64_vecCmpBr.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "arm64-apple-ios3.0.0"
define i32 @anyZero64(<4 x i16> %a) #0 { define i32 @anyZero64(<4 x i16> %a) #0 {
; CHECK: _anyZero64: ; CHECK: _anyZero64:
; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
; CHECK: [[LABEL]]: ; CHECK: [[LABEL]]:
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llvm/trunk/test/CodeGen/AArch64/arm64-vecFold.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -o - %s| FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp { define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp {
; CHECK-LABEL: foov16i8: ; CHECK-LABEL: foov16i8:
%vshrn_low_shift = lshr <8 x i16> %a0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %vshrn_low_shift = lshr <8 x i16> %a0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%vshrn_low = trunc <8 x i16> %vshrn_low_shift to <8 x i8> %vshrn_low = trunc <8 x i16> %vshrn_low_shift to <8 x i8>
%vshrn_high_shift = lshr <8 x i16> %b0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %vshrn_high_shift = lshr <8 x i16> %b0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%vshrn_high = trunc <8 x i16> %vshrn_high_shift to <8 x i8> %vshrn_high = trunc <8 x i16> %vshrn_high_shift to <8 x i8>
; CHECK: shrn.8b v0, v0, #5 ; CHECK: shrn.8b v0, v0, #5
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llvm/trunk/test/CodeGen/AArch64/arm64-vector-ext.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
;CHECK: @func30 ;CHECK: @func30
;CHECK: movi.4h v1, #1 ;CHECK: movi.4h v1, #1
;CHECK: and.8b v0, v0, v1 ;CHECK: and.8b v0, v0, v1
;CHECK: ushll.4s v0, v0, #0 ;CHECK: ushll.4s v0, v0, #0
;CHECK: str q0, [x0] ;CHECK: str q0, [x0]
;CHECK: ret ;CHECK: ret
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llvm/trunk/test/CodeGen/AArch64/arm64-vector-imm.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_orrimm: ; CHECK-LABEL: v_orrimm:
; CHECK-NOT: mov ; CHECK-NOT: mov
; CHECK-NOT: mvn ; CHECK-NOT: mvn
; CHECK: orr ; CHECK: orr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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llvm/trunk/test/CodeGen/AArch64/arm64-vector-insertion.ll

; RUN: llc -march=arm64 -mcpu=generic -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=generic -aarch64-neon-syntax=apple | FileCheck %s
define void @test0f(float* nocapture %x, float %a) #0 { define void @test0f(float* nocapture %x, float %a) #0 {
entry: entry:
%0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0 %0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0
%1 = bitcast float* %x to <4 x float>* %1 = bitcast float* %x to <4 x float>*
store <4 x float> %0, <4 x float>* %1, align 16 store <4 x float> %0, <4 x float>* %1, align 16
ret void ret void
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llvm/trunk/test/CodeGen/AArch64/arm64-vector-ldst.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
; rdar://9428579 ; rdar://9428579
%type1 = type { <16 x i8> } %type1 = type { <16 x i8> }
%type2 = type { <8 x i8> } %type2 = type { <8 x i8> }
%type3 = type { <4 x i16> } %type3 = type { <4 x i16> }
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llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define void @test_vext_s8() nounwind ssp { define void @test_vext_s8() nounwind ssp {
; CHECK-LABEL: test_vext_s8: ; CHECK-LABEL: test_vext_s8:
; CHECK: {{ext.8.*#1}} ; CHECK: {{ext.8.*#1}}
%xS8x8 = alloca <8 x i8>, align 8 %xS8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8 %__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8 %__b = alloca <8 x i8>, align 8
%tmp = load <8 x i8>, <8 x i8>* %xS8x8, align 8 %tmp = load <8 x i8>, <8 x i8>* %xS8x8, align 8
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llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
;;; Float vectors ;;; Float vectors
%v2f32 = type <2 x float> %v2f32 = type <2 x float>
; CHECK: test_v2f32.sqrt: ; CHECK: test_v2f32.sqrt:
define %v2f32 @test_v2f32.sqrt(%v2f32 %a) { define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
; CHECK: fsqrt.2s ; CHECK: fsqrt.2s
%1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a) %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
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llvm/trunk/test/CodeGen/AArch64/arm64-vhadd.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: shadd8b: ;CHECK-LABEL: shadd8b:
;CHECK: shadd.8b ;CHECK: shadd.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vhsub.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: shsub8b: ;CHECK-LABEL: shsub8b:
;CHECK: shsub.8b ;CHECK: shsub.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vmax.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: smax_8b: ;CHECK-LABEL: smax_8b:
;CHECK: smax.8b ;CHECK: smax.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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declare <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone declare <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone declare <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: smaxp_8b: ;CHECK-LABEL: smaxp_8b:
;CHECK: smaxp.8b ;CHECK: smaxp.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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declare <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone declare <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone declare <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone declare <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sminp_8b: ;CHECK-LABEL: sminp_8b:
;CHECK: sminp.8b ;CHECK: sminp.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vminmaxnm.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp { define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
; CHECK: fmaxnm.2s v0, v0, v1 ; CHECK: fmaxnm.2s v0, v0, v1
; CHECK: ret ; CHECK: ret
%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind %vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
ret <2 x float> %vmaxnm2.i ret <2 x float> %vmaxnm2.i
} }
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llvm/trunk/test/CodeGen/AArch64/arm64-vmovn.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @xtn8b(<8 x i16> %A) nounwind { define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
;CHECK-LABEL: xtn8b: ;CHECK-LABEL: xtn8b:
;CHECK-NOT: ld1 ;CHECK-NOT: ld1
;CHECK: xtn.8b v0, v0 ;CHECK: xtn.8b v0, v0
;CHECK-NEXT: ret ;CHECK-NEXT: ret
%tmp3 = trunc <8 x i16> %A to <8 x i8> %tmp3 = trunc <8 x i16> %A to <8 x i8>
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vmul.ll

; RUN: llc -asm-verbose=false < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -asm-verbose=false -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: smull8h: ;CHECK-LABEL: smull8h:
;CHECK: smull.8h ;CHECK: smull.8h
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
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llvm/trunk/test/CodeGen/AArch64/arm64-volatile.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define i64 @normal_load(i64* nocapture %bar) nounwind readonly { define i64 @normal_load(i64* nocapture %bar) nounwind readonly {
; CHECK: normal_load ; CHECK: normal_load
; CHECK: ldp ; CHECK: ldp
; CHECK-NEXT: add ; CHECK-NEXT: add
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%add.ptr = getelementptr inbounds i64, i64* %bar, i64 1 %add.ptr = getelementptr inbounds i64, i64* %bar, i64 1
%tmp = load i64, i64* %add.ptr, align 8 %tmp = load i64, i64* %add.ptr, align 8
%add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2 %add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2
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llvm/trunk/test/CodeGen/AArch64/arm64-vpopcnt.ll

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
target triple = "arm64-apple-ios"
; The non-byte ones used to fail with "Cannot select" ; The non-byte ones used to fail with "Cannot select"
; CHECK-LABEL: ctpopv8i8 ; CHECK-LABEL: ctpopv8i8
; CHECK: cnt.8b ; CHECK: cnt.8b
define <8 x i8> @ctpopv8i8(<8 x i8> %x) nounwind readnone { define <8 x i8> @ctpopv8i8(<8 x i8> %x) nounwind readnone {
%cnt = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %x) %cnt = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %x)
ret <8 x i8> %cnt ret <8 x i8> %cnt
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llvm/trunk/test/CodeGen/AArch64/arm64-vqadd.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sqadd8b: ;CHECK-LABEL: sqadd8b:
;CHECK: sqadd.8b ;CHECK: sqadd.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vqsub.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sqsub8b: ;CHECK-LABEL: sqsub8b:
;CHECK: sqsub.8b ;CHECK: sqsub.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vselect.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
;CHECK: @func63 ;CHECK: @func63
;CHECK: cmeq.4h v0, v0, v1 ;CHECK: cmeq.4h v0, v0, v1
;FIXME: currently, it will generate 3 instructions: ;FIXME: currently, it will generate 3 instructions:
; ushll.4s v0, v0, #0 ; ushll.4s v0, v0, #0
; shl.4s v0, v0, #31 ; shl.4s v0, v0, #31
; sshr.4s v0, v0, #31 ; sshr.4s v0, v0, #31
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llvm/trunk/test/CodeGen/AArch64/arm64-vsetcc_fp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define <2 x i32> @fcmp_one(<2 x float> %x, <2 x float> %y) nounwind optsize readnone { define <2 x i32> @fcmp_one(<2 x float> %x, <2 x float> %y) nounwind optsize readnone {
; CHECK-LABEL: fcmp_one: ; CHECK-LABEL: fcmp_one:
; CHECK-NEXT: fcmgt.2s [[REG:v[0-9]+]], v0, v1 ; CHECK-NEXT: fcmgt.2s [[REG:v[0-9]+]], v0, v1
; CHECK-NEXT: fcmgt.2s [[REG2:v[0-9]+]], v1, v0 ; CHECK-NEXT: fcmgt.2s [[REG2:v[0-9]+]], v1, v0
; CHECK-NEXT: orr.8b v0, [[REG2]], [[REG]] ; CHECK-NEXT: orr.8b v0, [[REG2]], [[REG]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = fcmp one <2 x float> %x, %y %tmp = fcmp one <2 x float> %x, %y
%or = sext <2 x i1> %tmp to <2 x i32> %or = sext <2 x i1> %tmp to <2 x i32>
ret <2 x i32> %or ret <2 x i32> %or
} }

llvm/trunk/test/CodeGen/AArch64/arm64-vshift.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sqshl8b: ;CHECK-LABEL: sqshl8b:
;CHECK: sqshl.8b ;CHECK: sqshl.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vshr.ll

; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 { define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: testShiftRightArith_v8i16: ; CHECK-LABEL: testShiftRightArith_v8i16:
; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]] ; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]] ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
entry: entry:
%a.addr = alloca <8 x i16>, align 16 %a.addr = alloca <8 x i16>, align 16
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llvm/trunk/test/CodeGen/AArch64/arm64-vsqrt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
;CHECK-LABEL: frecps_2s: ;CHECK-LABEL: frecps_2s:
;CHECK: frecps.2s ;CHECK: frecps.2s
%tmp1 = load <2 x float>, <2 x float>* %A %tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B %tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3 ret <2 x float> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vsra.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vsras8: ;CHECK-LABEL: vsras8:
;CHECK: ssra.8b ;CHECK: ssra.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
%tmp4 = add <8 x i8> %tmp1, %tmp3 %tmp4 = add <8 x i8> %tmp1, %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-vsub.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
;CHECK-LABEL: subhn8b: ;CHECK-LABEL: subhn8b:
;CHECK: subhn.8b ;CHECK: subhn.8b
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
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llvm/trunk/test/CodeGen/AArch64/arm64-xaluo.ll

; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-atomic-cfg-tidy=0 -disable-post-ra -verify-machineinstrs | FileCheck %s
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -disable-post-ra -verify-machineinstrs | FileCheck %s
; ;
; Get the actual value of the overflow bit. ; Get the actual value of the overflow bit.
; ;
define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) { define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
entry: entry:
; CHECK-LABEL: saddo1.i32 ; CHECK-LABEL: saddo1.i32
; CHECK: adds {{w[0-9]+}}, w0, w1 ; CHECK: adds {{w[0-9]+}}, w0, w1
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llvm/trunk/test/CodeGen/AArch64/arm64-zext.ll

; RUN: llc < %s -march=arm64 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp { define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
entry: entry:
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: add w0, w1, w0 ; CHECK: add w0, w1, w0
; CHECK: ret ; CHECK: ret
%add = add i32 %b, %a %add = add i32 %b, %a
%conv = zext i32 %add to i64 %conv = zext i32 %add to i64
ret i64 %conv ret i64 %conv
} }

llvm/trunk/test/CodeGen/AArch64/arm64-zextload-unscaled.ll

; RUN: llc -march=arm64 < %s | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
@var32 = global i32 0 @var32 = global i32 0
define void @test_zextloadi1_unscaled(i1* %base) { define void @test_zextloadi1_unscaled(i1* %base) {
; CHECK-LABEL: test_zextloadi1_unscaled: ; CHECK-LABEL: test_zextloadi1_unscaled:
; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7] ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
%addr = getelementptr i1, i1* %base, i32 -7 %addr = getelementptr i1, i1* %base, i32 -7
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llvm/trunk/test/CodeGen/AArch64/arm64-zip.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: vzipi8: ;CHECK-LABEL: vzipi8:
;CHECK: zip1.8b ;CHECK: zip1.8b
;CHECK: zip2.8b ;CHECK: zip2.8b
;CHECK-NEXT: add.8b ;CHECK-NEXT: add.8b
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
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llvm/trunk/test/CodeGen/AArch64/asm-large-immediate.ll

; RUN: llc -march=aarch64 -no-integrated-as < %s | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi -no-integrated-as | FileCheck %s
define void @test() { define void @test() {
entry: entry:
; CHECK: /* result: 68719476738 */ ; CHECK: /* result: 68719476738 */
tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
; CHECK: /* result: -68719476738 */ ; CHECK: /* result: -68719476738 */
tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
ret void ret void
} }

llvm/trunk/test/CodeGen/AArch64/branch-folder-merge-mmos.ll

; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu -stop-after branch-folder -o - < %s | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -stop-after branch-folder | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @foo(i32 %a, i32 %b, float* nocapture %foo_arr) #0 { define void @foo(i32 %a, i32 %b, float* nocapture %foo_arr) #0 {
; CHECK: (load 4 from %ir.arrayidx1.{{i[1-2]}}), (load 4 from %ir.arrayidx1.{{i[1-2]}}) ; CHECK: (load 4 from %ir.arrayidx1.{{i[1-2]}}), (load 4 from %ir.arrayidx1.{{i[1-2]}})
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
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llvm/trunk/test/CodeGen/AArch64/cmpwithshort.ll

; RUN: llc -O3 -march=aarch64 < %s | FileCheck %s ; RUN: llc < %s -O3 -mtriple=aarch64-eabi | FileCheck %s
define i16 @test_1cmp_signed_1(i16* %ptr1) { define i16 @test_1cmp_signed_1(i16* %ptr1) {
; CHECK-LABLE: @test_1cmp_signed_1 ; CHECK-LABLE: @test_1cmp_signed_1
; CHECK: ldrsh ; CHECK: ldrsh
; CHECK-NEXT: cmn ; CHECK-NEXT: cmn
entry: entry:
%addr = getelementptr inbounds i16, i16* %ptr1, i16 0 %addr = getelementptr inbounds i16, i16* %ptr1, i16 0
%val = load i16, i16* %addr, align 2 %val = load i16, i16* %addr, align 2
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llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; marked as external to prevent possible optimizations ; marked as external to prevent possible optimizations
@a = external global i32 @a = external global i32
@b = external global i32 @b = external global i32
@c = external global i32 @c = external global i32
@d = external global i32 @d = external global i32
; (a > 10 && b == c) || (a >= 10 && b == d) ; (a > 10 && b == c) || (a >= 10 && b == d)
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llvm/trunk/test/CodeGen/AArch64/complex-fp-to-int.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) { define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) {
; CHECK-LABEL: test_v2f32_to_signed_v2i64: ; CHECK-LABEL: test_v2f32_to_signed_v2i64:
; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s ; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
; CHECK: fcvtzs.2d v0, [[VAL64]] ; CHECK: fcvtzs.2d v0, [[VAL64]]
%val = fptosi <2 x float> %in to <2 x i64> %val = fptosi <2 x float> %in to <2 x i64>
ret <2 x i64> %val ret <2 x i64> %val
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llvm/trunk/test/CodeGen/AArch64/complex-int-to-fp.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; CHECK: autogen_SD19655 ; CHECK: autogen_SD19655
; CHECK: scvtf ; CHECK: scvtf
; CHECK: ret ; CHECK: ret
define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) { define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
%T = load <2 x i64>, <2 x i64>* %addr %T = load <2 x i64>, <2 x i64>* %addr
%F = sitofp <2 x i64> %T to <2 x float> %F = sitofp <2 x i64> %T to <2 x float>
store <2 x float> %F, <2 x float>* %addrfloat store <2 x float> %F, <2 x float>* %addrfloat
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llvm/trunk/test/CodeGen/AArch64/div_minsize.ll

; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
define i32 @testsize1(i32 %x) minsize nounwind { define i32 @testsize1(i32 %x) minsize nounwind {
entry: entry:
%div = sdiv i32 %x, 32 %div = sdiv i32 %x, 32
ret i32 %div ret i32 %div
; CHECK-LABEL: testsize1 ; CHECK-LABEL: testsize1
; CHECK: sdiv ; CHECK: sdiv
} }
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llvm/trunk/test/CodeGen/AArch64/large_shift.ll

; RUN: llc -march=aarch64 -o - %s ; RUN: llc -mtriple=arm64-unknown-unknown -o - %s
target triple = "arm64-unknown-unknown"
; Make sure we don't run into an assert in the aarch64 code selection when ; Make sure we don't run into an assert in the aarch64 code selection when
; DAGCombining fails. ; DAGCombining fails.
declare void @t() declare void @t()
define void @foo() { define void @foo() {
%c = bitcast i64 270458 to i64 %c = bitcast i64 270458 to i64
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llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll

; RUN: llc < %s -march=aarch64 -aarch64-neon-syntax=apple -aarch64-stp-suppress=false -verify-machineinstrs -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple -aarch64-stp-suppress=false -verify-machineinstrs -asm-verbose=false | FileCheck %s
; CHECK-LABEL: test_strd_sturd: ; CHECK-LABEL: test_strd_sturd:
; CHECK-NEXT: stp d0, d1, [x0, #-8] ; CHECK-NEXT: stp d0, d1, [x0, #-8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define void @test_strd_sturd(float* %ptr, <2 x float> %v1, <2 x float> %v2) #0 { define void @test_strd_sturd(float* %ptr, <2 x float> %v1, <2 x float> %v2) #0 {
%tmp1 = bitcast float* %ptr to <2 x float>* %tmp1 = bitcast float* %ptr to <2 x float>*
store <2 x float> %v2, <2 x float>* %tmp1, align 16 store <2 x float> %v2, <2 x float>* %tmp1, align 16
%add.ptr = getelementptr inbounds float, float* %ptr, i64 -2 %add.ptr = getelementptr inbounds float, float* %ptr, i64 -2
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llvm/trunk/test/CodeGen/AArch64/legalize-bug-bogus-cpu.ll

; RUN: llc -march=aarch64 -mcpu=bogus -o - %s ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=bogus
; Fix the bug in PR20557. Set mcpu to a bogus name, llc will crash in type ; Fix the bug in PR20557. Set mcpu to a bogus name, llc will crash in type
; legalization. ; legalization.
define <4 x float> @fneg4(<4 x float> %x) { define <4 x float> @fneg4(<4 x float> %x) {
%sub = fsub <4 x float> zeroinitializer, %x %sub = fsub <4 x float> zeroinitializer, %x
ret <4 x float> %sub ret <4 x float> %sub
} }

llvm/trunk/test/CodeGen/AArch64/lit.local.cfg

import re import re
if not 'AArch64' in config.root.targets: if not 'AArch64' in config.root.targets:
config.unsupported = True config.unsupported = True
# For now we don't test arm64-win32.
if re.search(r'cygwin|mingw32|win32|windows-gnu|windows-msvc', config.target_triple):
config.unsupported = True

llvm/trunk/test/CodeGen/AArch64/lower-range-metadata-func-call.ll

; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; and can be eliminated ; and can be eliminated
; CHECK-LABEL: {{^}}test_call_known_max_range: ; CHECK-LABEL: {{^}}test_call_known_max_range:
; CHECK: bl foo ; CHECK: bl foo
; CHECK-NOT: and ; CHECK-NOT: and
; CHECK: ret ; CHECK: ret
define i32 @test_call_known_max_range() #0 { define i32 @test_call_known_max_range() #0 {
entry: entry:
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llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll

; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
%structA = type { i128 } %structA = type { i128 }
@stubA = internal unnamed_addr constant %structA zeroinitializer, align 8 @stubA = internal unnamed_addr constant %structA zeroinitializer, align 8
; Make sure we don't hit llvm_unreachable. ; Make sure we don't hit llvm_unreachable.
define void @test1() { define void @test1() {
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
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llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll

; RUN: llc -mcpu cortex-a53 -march aarch64 %s -o - | FileCheck %s --check-prefix=A53 ; RUN: llc < %s -mcpu cortex-a53 -mtriple=aarch64-eabi | FileCheck %s --check-prefix=A53
; PR26827 - Merge stores causes wrong dependency. ; PR26827 - Merge stores causes wrong dependency.
%struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* } %struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* }
@gv0 = internal unnamed_addr global i32 0, align 4 @gv0 = internal unnamed_addr global i32 0, align 4
@gv1 = internal unnamed_addr global %struct1** null, align 8 @gv1 = internal unnamed_addr global %struct1** null, align 8
define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) { define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) {
;CHECK-LABEL: test ;CHECK-LABEL: test
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llvm/trunk/test/CodeGen/AArch64/merge-store.ll

; RUN: llc -mtriple=aarch64-unknown-unknown %s -mcpu=cyclone -o - | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK
; RUN: llc -march aarch64 %s -mattr=-slow-misaligned-128store -o - | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
@g0 = external global <3 x float>, align 16 @g0 = external global <3 x float>, align 16
@g1 = external global <3 x float>, align 4 @g1 = external global <3 x float>, align 4
; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4 ; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4
; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}} ; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}}
; CHECK: str d[[R0]] ; CHECK: str d[[R0]]
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llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll

; RUN: llc < %s -march=aarch64 | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi | FileCheck %s
; Convert mul x, pow2 to shift. ; Convert mul x, pow2 to shift.
; Convert mul x, pow2 +/- 1 to shift + add/sub. ; Convert mul x, pow2 +/- 1 to shift + add/sub.
define i32 @test2(i32 %x) { define i32 @test2(i32 %x) {
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
; CHECK: lsl w0, w0, #1 ; CHECK: lsl w0, w0, #1
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llvm/trunk/test/CodeGen/AArch64/no-quad-ldp-stp.ll

; RUN: llc < %s -march=aarch64 -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s
; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
; CHECK-LABEL: test_nopair_st ; CHECK-LABEL: test_nopair_st
; CHECK: str ; CHECK: str
; CHECK: stur ; CHECK: stur
; CHECK-NOT: stp ; CHECK-NOT: stp
define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) { define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
%tmp1 = bitcast double* %ptr to <2 x double>* %tmp1 = bitcast double* %ptr to <2 x double>*
store <2 x double> %v2, <2 x double>* %tmp1, align 16 store <2 x double> %v2, <2 x double>* %tmp1, align 16
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llvm/trunk/test/CodeGen/AArch64/nzcv-save.ll

; RUN: llc -verify-machineinstrs -march=aarch64 < %s | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-eabi | FileCheck %s
; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
; CHECK: msr NZCV, [[NZCV_SAVE]] ; CHECK: msr NZCV, [[NZCV_SAVE]]
; DAG ends up with two uses for the flags from an ADCS node, which means they ; DAG ends up with two uses for the flags from an ADCS node, which means they
; must be saved for later. ; must be saved for later.
define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp { define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
entry: entry:
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llvm/trunk/test/CodeGen/AArch64/postra-mi-sched.ll

; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s ; RUN: llc < %s -O3 -mtriple=aarch64-eabi -mcpu=cortex-a53 | FileCheck %s
; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the ; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
; post-RA MI scheduler will clean this up. ; post-RA MI scheduler will clean this up.
@d1 = common global double 0.000000e+00, align 8 @d1 = common global double 0.000000e+00, align 8
define i32 @test1(float %s2, float %s3, double %d, i32 %i2, i32 %i3) { define i32 @test1(float %s2, float %s3, double %d, i32 %i2, i32 %i3) {
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llvm/trunk/test/CodeGen/AArch64/rem_crash.ll

; RUN: llc < %s -march=aarch64 ; RUN: llc < %s -mtriple=aarch64-eabi
define i8 @test_minsize_uu8(i8 %x) minsize optsize { define i8 @test_minsize_uu8(i8 %x) minsize optsize {
entry: entry:
%0 = udiv i8 %x, 10 %0 = udiv i8 %x, 10
%1 = urem i8 %x, 10 %1 = urem i8 %x, 10
%res = add i8 %0, %1 %res = add i8 %0, %1
ret i8 %res ret i8 %res
} }
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llvm/trunk/test/CodeGen/AArch64/tailmerging_in_mbp.ll

; RUN: llc <%s -march=aarch64 -verify-machine-dom-info | FileCheck %s ; RUN: llc <%s -mtriple=aarch64-eabi -verify-machine-dom-info | FileCheck %s
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: LBB0_7: ; CHECK: LBB0_7:
; CHECK: b.hi ; CHECK: b.hi
; CHECK-NEXT: b ; CHECK-NEXT: b
; CHECK-NEXT: LBB0_8: ; CHECK-NEXT: LBB0_8:
; CHECK-NEXT: mov x8, x9 ; CHECK-NEXT: mov x8, x9
; CHECK-NEXT: LBB0_9: ; CHECK-NEXT: LBB0_9:
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llvm/trunk/test/CodeGen/AArch64/tbz-tbnz.ll

; RUN: llc -O1 -march=aarch64 < %s | FileCheck %s ; RUN: llc < %s -O1 -mtriple=aarch64-eabi | FileCheck %s
declare void @t() declare void @t()
define void @test1(i32 %a) { define void @test1(i32 %a) {
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
entry: entry:
%sub = add nsw i32 %a, -12 %sub = add nsw i32 %a, -12
%cmp = icmp slt i32 %sub, 0 %cmp = icmp slt i32 %sub, 0
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