Index: lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.td +++ lib/Target/AMDGPU/SIInstrInfo.td @@ -2291,6 +2291,8 @@ VOP2_REV { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); let SchedRW = sched; + let hasSideEffects = DefExec; + let isConvergent = DefExec; } let AssemblerPredicates = [isSICI] in { @@ -2298,6 +2300,7 @@ SIMCInstr { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); let hasSideEffects = DefExec; + let isConvergent = DefExec; let SchedRW = sched; let DecoderNamespace = "SICI"; let DisableDecoder = DisableSIDecoder; @@ -2310,6 +2313,7 @@ SIMCInstr { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); let hasSideEffects = DefExec; + let isConvergent = DefExec; let SchedRW = sched; let DecoderNamespace = "VI"; let DisableDecoder = DisableVIDecoder;