Index: lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- lib/Target/SystemZ/SystemZInstrInfo.td
+++ lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1685,12 +1685,12 @@
 def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
                           (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
 
-// Shift/rotate instructions only use the last 6 bits of the second operand
-// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the
-// last 16 bits.
 // Complexity is added so that we match this before we match NILF on the AND
 // operation alone.
 let AddedComplexity = 4 in {
+  // Shift/rotate instructions only use the last 6 bits of the second operand
+  // register, so we can safely use NILL (16 fewer bits than NILF) to only AND the
+  // last 16 bits.
   def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)),
             (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
 
@@ -1716,6 +1716,34 @@
             (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
 }
 
+let AddedComplexity = 5 in {
+  // If an AND operation doesn't change the last 6 bits before the result is
+  // used for a shift/rotate, we can remove it entirely.
+  def : Pat<(shl GR32:$val, (and GR32:$shift, imm32bottom6)),
+            (SLL GR32:$val, GR32:$shift, 0)>;
+
+  def : Pat<(sra GR32:$val, (and GR32:$shift, imm32bottom6)),
+            (SRA GR32:$val, GR32:$shift, 0)>;
+
+  def : Pat<(srl GR32:$val, (and GR32:$shift, imm32bottom6)),
+            (SRL GR32:$val, GR32:$shift, 0)>;
+
+  def : Pat<(shl GR64:$val, (and GR32:$shift, imm32bottom6)),
+            (SLLG GR64:$val, GR32:$shift, 0)>;
+
+  def : Pat<(sra GR64:$val, (and GR32:$shift, imm32bottom6)),
+            (SRAG GR64:$val, GR32:$shift, 0)>;
+
+  def : Pat<(srl GR64:$val, (and GR32:$shift, imm32bottom6)),
+            (SRLG GR64:$val, GR32:$shift, 0)>;
+
+  def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32bottom6)),
+            (RLL GR32:$val, GR32:$shift, 0)>;
+
+  def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32bottom6)),
+            (RLLG GR64:$val, GR32:$shift, 0)>;
+}
+
 // Peepholes for turning scalar operations into block operations.
 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 1>;
Index: lib/Target/SystemZ/SystemZOperands.td
===================================================================
--- lib/Target/SystemZ/SystemZOperands.td
+++ lib/Target/SystemZ/SystemZOperands.td
@@ -328,6 +328,11 @@
 
 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
 
+// Bottom 6 bits are all set
+def imm32bottom6 : Immediate<i32, [{
+  return (N->getZExtValue() & 0x3f) == 0x3f;
+}], NOOP_SDNodeXForm, "U32Imm">;
+
 // Full 32-bit immediates.  we need both signed and unsigned versions
 // because the assembler is picky.  E.g. AFI requires signed operands
 // while NILF requires unsigned ones.
Index: test/CodeGen/SystemZ/rot-01.ll
===================================================================
--- test/CodeGen/SystemZ/rot-01.ll
+++ test/CodeGen/SystemZ/rot-01.ll
@@ -21,9 +21,9 @@
 ; Test 64-bit rotate.
 define i64 @f2(i64 %val, i64 %amt) {
 ; CHECK-LABEL: f2:
-; CHECK: nill %r3, 63
+; CHECK: nill %r3, 31
 ; CHECK: rllg %r2, %r2, 0(%r3)
-  %mod = urem i64 %amt, 64
+  %mod = urem i64 %amt, 32
 
   %inv = sub i64 64, %mod
   %parta = shl i64 %val, %mod
Index: test/CodeGen/SystemZ/rot-02.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/rot-02.ll
@@ -0,0 +1,68 @@
+; Test removal of AND operations that don't affect last 6 bits of rotate amount
+; operand.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test that AND is not removed when some lower 6 bits are not set.
+define i32 @f1(i32 %val, i32 %amt) {
+; CHECK-LABEL: f1:
+; CHECK: nil{{[lf]}} %r3, 31
+; CHECK: rll %r2, %r2, 0(%r3)
+  %and = and i32 %amt, 31
+
+  %inv = sub i32 32, %and
+  %parta = shl i32 %val, %and
+  %partb = lshr i32 %val, %inv
+
+  %rotl = or i32 %parta, %partb
+
+  ret i32 %rotl
+}
+
+; Test removal of AND mask with only bottom 6 bits set.
+define i32 @f2(i32 %val, i32 %amt) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: rll %r2, %r2, 0(%r3)
+  %and = and i32 %amt, 63
+
+  %inv = sub i32 32, %and
+  %parta = shl i32 %val, %and
+  %partb = lshr i32 %val, %inv
+
+  %rotl = or i32 %parta, %partb
+
+  ret i32 %rotl
+}
+
+; Test removal of AND mask including but not limited to bottom 6 bits.
+define i32 @f3(i32 %val, i32 %amt) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: nil{{[lf]}} %r3, 255
+; CHECK: rll %r2, %r2, 0(%r3)
+  %and = and i32 %amt, 255
+
+  %inv = sub i32 32, %and
+  %parta = shl i32 %val, %and
+  %partb = lshr i32 %val, %inv
+
+  %rotl = or i32 %parta, %partb
+
+  ret i32 %rotl
+}
+
+; Test removal of AND mask from RLLG.
+define i64 @f4(i64 %val, i64 %amt) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: rllg %r2, %r2, 0(%r3)
+  %and = and i64 %amt, 63
+
+  %inv = sub i64 64, %and
+  %parta = shl i64 %val, %and
+  %partb = lshr i64 %val, %inv
+
+  %rotl = or i64 %parta, %partb
+
+  ret i64 %rotl
+}
Index: test/CodeGen/SystemZ/shift-12.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/shift-12.ll
@@ -0,0 +1,84 @@
+; Test removal of AND operations that don't affect last 6 bits of shift amount
+; operand.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test that AND is not removed when some lower 6 bits are not set.
+define i32 @f1(i32 %a, i32 %sh) {
+; CHECK-LABEL: f1:
+; CHECK: nil{{[lf]}} %r3, 31
+; CHECK: sll %r2, 0(%r3)
+  %and = and i32 %sh, 31
+  %shift = shl i32 %a, %and
+  ret i32 %shift
+}
+
+; Test removal of AND mask with only bottom 6 bits set.
+define i32 @f2(i32 %a, i32 %sh) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: sll %r2, 0(%r3)
+  %and = and i32 %sh, 63
+  %shift = shl i32 %a, %and
+  ret i32 %shift
+}
+
+; Test removal of AND mask including but not limited to bottom 6 bits.
+define i32 @f3(i32 %a, i32 %sh) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: nil{{[lf]}} %r3, 255
+; CHECK: sll %r2, 0(%r3)
+  %and = and i32 %sh, 255
+  %shift = shl i32 %a, %and
+  ret i32 %shift
+}
+
+; Test removal of AND mask from SRA.
+define i32 @f4(i32 %a, i32 %sh) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: sra %r2, 0(%r3)
+  %and = and i32 %sh, 63
+  %shift = ashr i32 %a, %and
+  ret i32 %shift
+}
+
+; Test removal of AND mask from SRL.
+define i32 @f5(i32 %a, i32 %sh) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: srl %r2, 0(%r3)
+  %and = and i32 %sh, 63
+  %shift = lshr i32 %a, %and
+  ret i32 %shift
+}
+
+; Test removal of AND mask from SLLG.
+define i64 @f6(i64 %a, i64 %sh) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: sllg %r2, %r2, 0(%r3)
+  %and = and i64 %sh, 63
+  %shift = shl i64 %a, %and
+  ret i64 %shift
+}
+
+; Test removal of AND mask from SRAG.
+define i64 @f7(i64 %a, i64 %sh) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: srag %r2, %r2, 0(%r3)
+  %and = and i64 %sh, 63
+  %shift = ashr i64 %a, %and
+  ret i64 %shift
+}
+
+; Test removal of AND mask from SRLG.
+define i64 @f8(i64 %a, i64 %sh) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: nil{{[lf]}} %r3, 63
+; CHECK: srlg %r2, %r2, 0(%r3)
+  %and = and i64 %sh, 63
+  %shift = lshr i64 %a, %and
+  ret i64 %shift
+}