Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -222,8 +222,8 @@
   return UseSubRegLiveness;
 }
 
-unsigned char PPCSubtarget::classifyGlobalReference(
-    const GlobalValue *GV) const {
+unsigned char
+PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
   // Note that currently we don't generate non-pic references.
   // If a caller wants that, this will have to be updated.
 
@@ -231,23 +231,9 @@
   if (TM.getCodeModel() == CodeModel::Large)
     return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
 
-  unsigned char flags = PPCII::MO_PIC_FLAG;
-
-  // Only if the relocation mode is PIC do we have to worry about
-  // interposition. In all other cases we can use a slightly looser standard to
-  // decide how to access the symbol.
-  if (TM.getRelocationModel() == Reloc::PIC_) {
-    // If it's local, or it's non-default, it can't be interposed.
-    if (!GV->hasLocalLinkage() &&
-        GV->hasDefaultVisibility()) {
-      flags |= PPCII::MO_NLP_FLAG;
-    }
-    return flags;
-  }
-
-  if (GV->isStrongDefinitionForLinker())
-    return flags;
-  return flags | PPCII::MO_NLP_FLAG;
+  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
+    return PPCII::MO_PIC_FLAG;
+  return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
 }
 
 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
Index: lib/Target/TargetMachine.cpp
===================================================================
--- lib/Target/TargetMachine.cpp
+++ lib/Target/TargetMachine.cpp
@@ -145,9 +145,12 @@
     if (GV && !GV->isDeclarationForLinker())
       return true;
 
-    bool IsTLS = GV && GV->isThreadLocal();
     // Check if we can use copy relocations.
-    if (!IsTLS && (RM == Reloc::Static || CanUseCopyRelocWithPIE))
+    bool IsTLS = GV && GV->isThreadLocal();
+    Triple::ArchType Arch = TT.getArch();
+    bool IsPPC =
+        Arch == Triple::ppc || Arch == Triple::ppc64 || Arch == Triple::ppc64le;
+    if (!IsTLS && !IsPPC && (RM == Reloc::Static || CanUseCopyRelocWithPIE))
       return true;
   }
 
Index: test/CodeGen/PowerPC/fast-isel-load-store.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-load-store.ll
+++ test/CodeGen/PowerPC/fast-isel-load-store.ll
@@ -196,7 +196,7 @@
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: addis
-; ELF64: ld
+; ELF64: addi
 ; ELF64: addi
 ; ELF64: lis
 ; ELF64: ori
Index: test/CodeGen/PowerPC/mcm-13.ll
===================================================================
--- test/CodeGen/PowerPC/mcm-13.ll
+++ test/CodeGen/PowerPC/mcm-13.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck --check-prefix=MEDIUM %s
 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
 
 ; Test correct code generation for medium and large code model
@@ -25,3 +25,9 @@
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
+
+; MEDIUM-LABEL: test_weak:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, wi@toc@ha
+; MEDIUM: addi [[REG1]], [[REG1]], wi@toc@l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG1]])
Index: test/CodeGen/PowerPC/mcm-6.ll
===================================================================
--- test/CodeGen/PowerPC/mcm-6.ll
+++ test/CodeGen/PowerPC/mcm-6.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck --check-prefix=MEDIUM %s
 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
 
 ; Test correct code generation for medium and large code model
@@ -26,3 +26,10 @@
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc [[VAR:[a-z0-9A-Z_.]+]][TC],{{[a-z0-9A-Z_.]+}}
 ; CHECK: .comm [[VAR]],4,4
+
+; MEDIUM-LABEL: test_tentative:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, ti@toc@ha
+; MEDIUM: addi [[REG1]], [[REG1]], ti@toc@l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: .comm ti,4,4
Index: test/CodeGen/PowerPC/mcm-obj.ll
===================================================================
--- test/CodeGen/PowerPC/mcm-obj.ll
+++ test/CodeGen/PowerPC/mcm-obj.ll
@@ -108,11 +108,10 @@
   ret i32 %0
 }
 
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
-; accessing tentatively declared variable ti.
+; Verify generation of relocations foraccessing variable ti.
 ;
 ; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM6]]
 ;
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
Index: test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
===================================================================
--- test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -89,9 +89,9 @@
   %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat.splat
-; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l
+; CHECK: addi [[REG1:[0-9]+]], [[REG1]], d@toc@l
 ; CHECK: lxvdsx 34, 0, [[REG1]]
-; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l
+; CHECK-LE: addi [[REG1:[0-9]+]], [[REG1]], d@toc@l
 ; CHECK-LE: lxvdsx 34, 0, [[REG1]]
 }
 
Index: test/CodeGen/PowerPC/ppc64le-aggregates.ll
===================================================================
--- test/CodeGen/PowerPC/ppc64le-aggregates.ll
+++ test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -264,7 +264,7 @@
   ret void
 }
 ; CHECK-LABEL: @caller2
-; CHECK: ld {{[0-9]+}}, .LC
+; CHECK: addis {{[0-9]+}}, 2, g2@toc@ha
 ; CHECK-DAG: lfs 1, 0({{[0-9]+}})
 ; CHECK-DAG: lfs 2, 4({{[0-9]+}})
 ; CHECK-DAG: lfs 3, 8({{[0-9]+}})
Index: test/CodeGen/PowerPC/ppcf128-endian.ll
===================================================================
--- test/CodeGen/PowerPC/ppcf128-endian.ll
+++ test/CodeGen/PowerPC/ppcf128-endian.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx -relocation-model=pic < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"