Index: include/llvm/Target/TargetLowering.h =================================================================== --- include/llvm/Target/TargetLowering.h +++ include/llvm/Target/TargetLowering.h @@ -2159,7 +2159,7 @@ /// Replace/modify any TargetFrameIndex operands with a targte-dependent /// sequence of memory operands that is recognized by PrologEpilogInserter. - MachineBasicBlock *emitPatchPoint(MachineInstr *MI, + MachineBasicBlock *emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const; }; @@ -3034,14 +3034,14 @@ /// As long as the returned basic block is different (i.e., we created a new /// one), the custom inserter is free to modify the rest of \p MBB. virtual MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const; /// This method should be implemented by targets that mark instructions with /// the 'hasPostISelHook' flag. These instructions must be adjusted after /// instruction selection by target hooks. e.g. To fill in optional defs for /// ARM 's' setting instructions. - virtual void - AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; + virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, + SDNode *Node) const; /// If this function returns true, SelectionDAGBuilder emits a /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. Index: lib/CodeGen/ExpandISelPseudos.cpp =================================================================== --- lib/CodeGen/ExpandISelPseudos.cpp +++ lib/CodeGen/ExpandISelPseudos.cpp @@ -58,8 +58,7 @@ // If MI is a pseudo, expand it. if (MI->usesCustomInsertionHook()) { Changed = true; - MachineBasicBlock *NewMBB = - TLI->EmitInstrWithCustomInserter(MI, MBB); + MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(*MI, MBB); // The expansion may involve new basic blocks. if (NewMBB != MBB) { MBB = NewMBB; Index: lib/CodeGen/SelectionDAG/InstrEmitter.cpp =================================================================== --- lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -875,7 +875,7 @@ // Run post-isel target hook to adjust this instruction if needed. if (II.hasPostISelHook()) - TLI->AdjustInstrPostInstrSelection(MIB, Node); + TLI->AdjustInstrPostInstrSelection(*MIB, Node); } /// EmitSpecialNode - Generate machine code for a target-independent node and Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -331,7 +331,7 @@ // are modified, the method should insert pairs of into the // DenseMap. MachineBasicBlock * -TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const { #ifndef NDEBUG dbgs() << "If a target marks an instruction with " @@ -341,9 +341,9 @@ llvm_unreachable(nullptr); } -void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, +void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { - assert(!MI->hasPostISelHook() && + assert(!MI.hasPostISelHook() && "If a target marks an instruction with 'hasPostISelHook', " "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); } Index: lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- lib/CodeGen/TargetLoweringBase.cpp +++ lib/CodeGen/TargetLoweringBase.cpp @@ -1172,9 +1172,10 @@ /// Replace/modify any TargetFrameIndex operands with a targte-dependent /// sequence of memory operands that is recognized by PrologEpilogInserter. -MachineBasicBlock* -TargetLoweringBase::emitPatchPoint(MachineInstr *MI, +MachineBasicBlock * +TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, MachineBasicBlock *MBB) const { + MachineInstr *MI = &InitialMI; MachineFunction &MF = *MI->getParent()->getParent(); MachineFrameInfo &MFI = *MF.getFrameInfo(); Index: lib/Target/AArch64/AArch64ISelLowering.h =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.h +++ lib/Target/AArch64/AArch64ISelLowering.h @@ -276,11 +276,11 @@ SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; - MachineBasicBlock *EmitF128CSEL(MachineInstr *MI, + MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -970,7 +970,7 @@ } MachineBasicBlock * -AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, +AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *MBB) const { // We materialise the F128CSEL pseudo-instruction as some control flow and a // phi node: @@ -987,14 +987,14 @@ MachineFunction *MF = MBB->getParent(); const TargetInstrInfo *TII = Subtarget->getInstrInfo(); const BasicBlock *LLVM_BB = MBB->getBasicBlock(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction::iterator It = ++MBB->getIterator(); - unsigned DestReg = MI->getOperand(0).getReg(); - unsigned IfTrueReg = MI->getOperand(1).getReg(); - unsigned IfFalseReg = MI->getOperand(2).getReg(); - unsigned CondCode = MI->getOperand(3).getImm(); - bool NZCVKilled = MI->getOperand(4).isKill(); + unsigned DestReg = MI.getOperand(0).getReg(); + unsigned IfTrueReg = MI.getOperand(1).getReg(); + unsigned IfFalseReg = MI.getOperand(2).getReg(); + unsigned CondCode = MI.getOperand(3).getImm(); + bool NZCVKilled = MI.getOperand(4).isKill(); MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB); @@ -1025,17 +1025,16 @@ .addReg(IfFalseReg) .addMBB(MBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return EndBB; } -MachineBasicBlock * -AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { +MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { default: #ifndef NDEBUG - MI->dump(); + MI.dump(); #endif llvm_unreachable("Unexpected instruction for custom inserter!"); Index: lib/Target/AMDGPU/R600ISelLowering.h =================================================================== --- lib/Target/AMDGPU/R600ISelLowering.h +++ lib/Target/AMDGPU/R600ISelLowering.h @@ -28,8 +28,9 @@ const R600Subtarget *getSubtarget() const; - MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock * BB) const override; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; void ReplaceNodeResults(SDNode * N, Index: lib/Target/AMDGPU/R600ISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/R600ISelLowering.cpp +++ lib/Target/AMDGPU/R600ISelLowering.cpp @@ -207,65 +207,63 @@ return std::next(I)->getOpcode() == AMDGPU::RETURN; } -MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( - MachineInstr * MI, MachineBasicBlock * BB) const { +MachineBasicBlock * +R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const { MachineFunction * MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); - MachineBasicBlock::iterator I = *MI; + MachineBasicBlock::iterator I = MI; const R600InstrInfo *TII = getSubtarget()->getInstrInfo(); - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: // Replace LDS_*_RET instruction that don't have any uses with the // equivalent LDS_*_NORET instruction. - if (TII->isLDSRetInstr(MI->getOpcode())) { - int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); + if (TII->isLDSRetInstr(MI.getOpcode())) { + int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); assert(DstIdx != -1); MachineInstrBuilder NewMI; // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add // LDS_1A2D support and remove this special case. - if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) || - MI->getOpcode() == AMDGPU::LDS_CMPST_RET) + if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) || + MI.getOpcode() == AMDGPU::LDS_CMPST_RET) return BB; NewMI = BuildMI(*BB, I, BB->findDebugLoc(I), - TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode()))); - for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) { - NewMI.addOperand(MI->getOperand(i)); + TII->get(AMDGPU::getLDSNoRetOp(MI.getOpcode()))); + for (unsigned i = 1, e = MI.getNumOperands(); i < e; ++i) { + NewMI.addOperand(MI.getOperand(i)); } } else { return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); } break; case AMDGPU::CLAMP_R600: { - MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, - AMDGPU::MOV, - MI->getOperand(0).getReg(), - MI->getOperand(1).getReg()); + MachineInstr *NewMI = TII->buildDefaultInstruction( + *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(), + MI.getOperand(1).getReg()); TII->addFlag(*NewMI, 0, MO_FLAG_CLAMP); break; } case AMDGPU::FABS_R600: { - MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, - AMDGPU::MOV, - MI->getOperand(0).getReg(), - MI->getOperand(1).getReg()); + MachineInstr *NewMI = TII->buildDefaultInstruction( + *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(), + MI.getOperand(1).getReg()); TII->addFlag(*NewMI, 0, MO_FLAG_ABS); break; } case AMDGPU::FNEG_R600: { - MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, - AMDGPU::MOV, - MI->getOperand(0).getReg(), - MI->getOperand(1).getReg()); + MachineInstr *NewMI = TII->buildDefaultInstruction( + *BB, I, AMDGPU::MOV, MI.getOperand(0).getReg(), + MI.getOperand(1).getReg()); TII->addFlag(*NewMI, 0, MO_FLAG_NEG); break; } case AMDGPU::MASK_WRITE: { - unsigned maskedRegister = MI->getOperand(0).getReg(); + unsigned maskedRegister = MI.getOperand(0).getReg(); assert(TargetRegisterInfo::isVirtualRegister(maskedRegister)); MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); TII->addFlag(*defInstr, 0, MO_FLAG_MASK); @@ -273,56 +271,57 @@ } case AMDGPU::MOV_IMM_F32: - TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), - MI->getOperand(1).getFPImm()->getValueAPF() - .bitcastToAPInt().getZExtValue()); + TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1) + .getFPImm() + ->getValueAPF() + .bitcastToAPInt() + .getZExtValue()); break; case AMDGPU::MOV_IMM_I32: - TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), - MI->getOperand(1).getImm()); + TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), + MI.getOperand(1).getImm()); break; case AMDGPU::MOV_IMM_GLOBAL_ADDR: { //TODO: Perhaps combine this instruction with the next if possible - auto MIB = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV, - MI->getOperand(0).getReg(), - AMDGPU::ALU_LITERAL_X); + auto MIB = TII->buildDefaultInstruction( + *BB, MI, AMDGPU::MOV, MI.getOperand(0).getReg(), AMDGPU::ALU_LITERAL_X); int Idx = TII->getOperandIdx(*MIB, AMDGPU::OpName::literal); //TODO: Ugh this is rather ugly - MIB->getOperand(Idx) = MI->getOperand(1); + MIB->getOperand(Idx) = MI.getOperand(1); break; } case AMDGPU::CONST_COPY: { - MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV, - MI->getOperand(0).getReg(), AMDGPU::ALU_CONST); + MachineInstr *NewMI = TII->buildDefaultInstruction( + *BB, MI, AMDGPU::MOV, MI.getOperand(0).getReg(), AMDGPU::ALU_CONST); TII->setImmOperand(*NewMI, AMDGPU::OpName::src0_sel, - MI->getOperand(1).getImm()); + MI.getOperand(1).getImm()); break; } case AMDGPU::RAT_WRITE_CACHELESS_32_eg: case AMDGPU::RAT_WRITE_CACHELESS_64_eg: case AMDGPU::RAT_WRITE_CACHELESS_128_eg: { - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)) - .addImm(isEOP(I)); // Set End of program bit + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode())) + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(1)) + .addImm(isEOP(I)); // Set End of program bit break; } case AMDGPU::RAT_STORE_TYPED_eg: { - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)) - .addOperand(MI->getOperand(2)) - .addImm(isEOP(I)); // Set End of program bit + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode())) + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(1)) + .addOperand(MI.getOperand(2)) + .addImm(isEOP(I)); // Set End of program bit break; } case AMDGPU::TXD: { unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); - MachineOperand &RID = MI->getOperand(4); - MachineOperand &SID = MI->getOperand(5); - unsigned TextureId = MI->getOperand(6).getImm(); + MachineOperand &RID = MI.getOperand(4); + MachineOperand &SID = MI.getOperand(5); + unsigned TextureId = MI.getOperand(6).getImm(); unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3; unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1; @@ -355,75 +354,77 @@ CTZ = 0; break; } - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0) - .addOperand(MI->getOperand(3)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW); - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1) - .addOperand(MI->getOperand(2)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), + T0) + .addOperand(MI.getOperand(3)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), + T1) + .addOperand(MI.getOperand(2)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW) - .addReg(T0, RegState::Implicit) - .addReg(T1, RegState::Implicit); + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(1)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW) + .addReg(T0, RegState::Implicit) + .addReg(T1, RegState::Implicit); break; } case AMDGPU::TXD_SHADOW: { unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); - MachineOperand &RID = MI->getOperand(4); - MachineOperand &SID = MI->getOperand(5); - unsigned TextureId = MI->getOperand(6).getImm(); + MachineOperand &RID = MI.getOperand(4); + MachineOperand &SID = MI.getOperand(5); + unsigned TextureId = MI.getOperand(6).getImm(); unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3; unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1; @@ -457,99 +458,101 @@ break; } - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0) - .addOperand(MI->getOperand(3)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW); - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1) - .addOperand(MI->getOperand(2)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), + T0) + .addOperand(MI.getOperand(3)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), + T1) + .addOperand(MI.getOperand(2)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G)) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)) - .addImm(SrcX) - .addImm(SrcY) - .addImm(SrcZ) - .addImm(SrcW) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(0) - .addImm(1) - .addImm(2) - .addImm(3) - .addOperand(RID) - .addOperand(SID) - .addImm(CTX) - .addImm(CTY) - .addImm(CTZ) - .addImm(CTW) - .addReg(T0, RegState::Implicit) - .addReg(T1, RegState::Implicit); + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(1)) + .addImm(SrcX) + .addImm(SrcY) + .addImm(SrcZ) + .addImm(SrcW) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(0) + .addImm(1) + .addImm(2) + .addImm(3) + .addOperand(RID) + .addOperand(SID) + .addImm(CTX) + .addImm(CTY) + .addImm(CTZ) + .addImm(CTW) + .addReg(T0, RegState::Implicit) + .addReg(T1, RegState::Implicit); break; } case AMDGPU::BRANCH: - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) - .addOperand(MI->getOperand(0)); - break; + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) + .addOperand(MI.getOperand(0)); + break; case AMDGPU::BRANCH_COND_f32: { MachineInstr *NewMI = - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), - AMDGPU::PREDICATE_BIT) - .addOperand(MI->getOperand(1)) - .addImm(OPCODE_IS_NOT_ZERO) - .addImm(0); // Flags + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), + AMDGPU::PREDICATE_BIT) + .addOperand(MI.getOperand(1)) + .addImm(OPCODE_IS_NOT_ZERO) + .addImm(0); // Flags TII->addFlag(*NewMI, 0, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND)) - .addOperand(MI->getOperand(0)) - .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); + .addOperand(MI.getOperand(0)) + .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); break; } case AMDGPU::BRANCH_COND_i32: { MachineInstr *NewMI = - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), - AMDGPU::PREDICATE_BIT) - .addOperand(MI->getOperand(1)) + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), + AMDGPU::PREDICATE_BIT) + .addOperand(MI.getOperand(1)) .addImm(OPCODE_IS_NOT_ZERO_INT) .addImm(0); // Flags TII->addFlag(*NewMI, 0, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND)) - .addOperand(MI->getOperand(0)) - .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); + .addOperand(MI.getOperand(0)) + .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); break; } @@ -557,7 +560,7 @@ case AMDGPU::R600_ExportSwz: { // Instruction is left unmodified if its not the last one of its type bool isLastInstructionOfItsType = true; - unsigned InstExportType = MI->getOperand(1).getImm(); + unsigned InstExportType = MI.getOperand(1).getImm(); for (MachineBasicBlock::iterator NextExportInst = std::next(I), EndBlock = BB->end(); NextExportInst != EndBlock; NextExportInst = std::next(NextExportInst)) { @@ -574,17 +577,17 @@ bool EOP = isEOP(I); if (!EOP && !isLastInstructionOfItsType) return BB; - unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40; - BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(1)) - .addOperand(MI->getOperand(2)) - .addOperand(MI->getOperand(3)) - .addOperand(MI->getOperand(4)) - .addOperand(MI->getOperand(5)) - .addOperand(MI->getOperand(6)) - .addImm(CfInst) - .addImm(EOP); + unsigned CfInst = (MI.getOpcode() == AMDGPU::EG_ExportSwz) ? 84 : 40; + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode())) + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(1)) + .addOperand(MI.getOperand(2)) + .addOperand(MI.getOperand(3)) + .addOperand(MI.getOperand(4)) + .addOperand(MI.getOperand(5)) + .addOperand(MI.getOperand(6)) + .addImm(CfInst) + .addImm(EOP); break; } case AMDGPU::RETURN: { @@ -598,7 +601,7 @@ } } - MI->eraseFromParent(); + MI.eraseFromParent(); return BB; } Index: lib/Target/AMDGPU/SIISelLowering.h =================================================================== --- lib/Target/AMDGPU/SIISelLowering.h +++ lib/Target/AMDGPU/SIISelLowering.h @@ -123,8 +123,9 @@ unsigned getRegisterByName(const char* RegName, EVT VT, SelectionDAG &DAG) const override; - MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, - MachineBasicBlock * BB) const override; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; bool enableAggressiveFMAFusion(EVT VT) const override; EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override; @@ -133,7 +134,7 @@ SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; - void AdjustInstrPostInstrSelection(MachineInstr *MI, + void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override; int32_t analyzeImmediate(const SDNode *N) const; Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -1064,15 +1064,16 @@ + StringRef(RegName) + "\".")); } -MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( - MachineInstr *MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { +MachineBasicBlock * +SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { case AMDGPU::SI_INIT_M0: { const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); - BuildMI(*BB, MI->getIterator(), MI->getDebugLoc(), + BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) - .addOperand(MI->getOperand(0)); - MI->eraseFromParent(); + .addOperand(MI.getOperand(0)); + MI.eraseFromParent(); break; } case AMDGPU::BRANCH: @@ -1082,11 +1083,11 @@ MachineFunction *MF = BB->getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); - DebugLoc DL = MI->getDebugLoc(); - BuildMI (*BB, MI, DL, TII->get(AMDGPU::S_MOVK_I32)) - .addOperand(MI->getOperand(0)) - .addImm(MFI->LDSSize); - MI->eraseFromParent(); + DebugLoc DL = MI.getDebugLoc(); + BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOVK_I32)) + .addOperand(MI.getOperand(0)) + .addImm(MFI->LDSSize); + MI.eraseFromParent(); return BB; } default: @@ -3215,22 +3216,22 @@ /// \brief Assign the register class depending on the number of /// bits set in the writemask -void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, +void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); - MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); - if (TII->isVOP3(MI->getOpcode())) { + if (TII->isVOP3(MI.getOpcode())) { // Make sure constant bus requirements are respected. - TII->legalizeOperandsVOP3(MRI, *MI); + TII->legalizeOperandsVOP3(MRI, MI); return; } - if (TII->isMIMG(*MI)) { - unsigned VReg = MI->getOperand(0).getReg(); - unsigned DmaskIdx = MI->getNumOperands() == 12 ? 3 : 4; - unsigned Writemask = MI->getOperand(DmaskIdx).getImm(); + if (TII->isMIMG(MI)) { + unsigned VReg = MI.getOperand(0).getReg(); + unsigned DmaskIdx = MI.getNumOperands() == 12 ? 3 : 4; + unsigned Writemask = MI.getOperand(DmaskIdx).getImm(); unsigned BitsSet = 0; for (unsigned i = 0; i < 4; ++i) BitsSet += Writemask & (1 << i) ? 1 : 0; @@ -3243,18 +3244,18 @@ case 3: RC = &AMDGPU::VReg_96RegClass; break; } - unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); - MI->setDesc(TII->get(NewOpcode)); + unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet); + MI.setDesc(TII->get(NewOpcode)); MRI.setRegClass(VReg, RC); return; } // Replace unused atomics with the no return version. - int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode()); + int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode()); if (NoRetAtomicOp != -1) { if (!Node->hasAnyUseOfValue(0)) { - MI->setDesc(TII->get(NoRetAtomicOp)); - MI->RemoveOperand(0); + MI.setDesc(TII->get(NoRetAtomicOp)); + MI.RemoveOperand(0); return; } @@ -3268,17 +3269,17 @@ Node->use_begin()->isMachineOpcode() && Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG && !Node->use_begin()->hasAnyUseOfValue(0))) { - unsigned Def = MI->getOperand(0).getReg(); + unsigned Def = MI.getOperand(0).getReg(); // Change this into a noret atomic. - MI->setDesc(TII->get(NoRetAtomicOp)); - MI->RemoveOperand(0); + MI.setDesc(TII->get(NoRetAtomicOp)); + MI.RemoveOperand(0); // If we only remove the def operand from the atomic instruction, the // extract_subreg will be left with a use of a vreg without a def. // So we need to insert an implicit_def to avoid machine verifier // errors. - BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), + BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AMDGPU::IMPLICIT_DEF), Def); } return; Index: lib/Target/ARM/ARMISelLowering.h =================================================================== --- lib/Target/ARM/ARMISelLowering.h +++ lib/Target/ARM/ARMISelLowering.h @@ -253,10 +253,10 @@ EVT VT) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *MBB) const override; + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; - void AdjustInstrPostInstrSelection(MachineInstr *MI, + void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override; SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; @@ -664,20 +664,19 @@ SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; - void SetupEntryBlockForSjLj(MachineInstr *MI, - MachineBasicBlock *MBB, + void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI) const; - void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const; + void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; - bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; + bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitStructByval(MachineInstr *MI, + MachineBasicBlock *EmitStructByval(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI, + MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *EmitLowered__dbzchk(MachineInstr *MI, + MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, MachineBasicBlock *MBB) const; }; Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -7275,11 +7275,12 @@ /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and /// registers the function context. -void ARMTargetLowering:: -SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, - MachineBasicBlock *DispatchBB, int FI) const { +void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI, + MachineBasicBlock *MBB, + MachineBasicBlock *DispatchBB, + int FI) const { const TargetInstrInfo *TII = Subtarget->getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); MachineRegisterInfo *MRI = &MF->getRegInfo(); MachineConstantPool *MCP = MF->getConstantPool(); @@ -7390,10 +7391,10 @@ } } -void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI, +void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetInstrInfo *TII = Subtarget->getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); MachineRegisterInfo *MRI = &MF->getRegInfo(); MachineFrameInfo *MFI = MF->getFrameInfo(); @@ -7775,7 +7776,7 @@ (*I)->setIsEHPad(false); // The instruction is gone now. - MI->eraseFromParent(); + MI.eraseFromParent(); } static @@ -7827,7 +7828,7 @@ /// Emit a post-increment load operation with given size. The instructions /// will be added to BB at Pos. -static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos, +static void emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) { @@ -7859,7 +7860,7 @@ /// Emit a post-increment store operation with given size. The instructions /// will be added to BB at Pos. -static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos, +static void emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) { @@ -7888,7 +7889,7 @@ } MachineBasicBlock * -ARMTargetLowering::EmitStructByval(MachineInstr *MI, +ARMTargetLowering::EmitStructByval(MachineInstr &MI, MachineBasicBlock *BB) const { // This pseudo instruction has 3 operands: dst, src, size // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold(). @@ -7897,11 +7898,11 @@ const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = ++BB->getIterator(); - unsigned dest = MI->getOperand(0).getReg(); - unsigned src = MI->getOperand(1).getReg(); - unsigned SizeVal = MI->getOperand(2).getImm(); - unsigned Align = MI->getOperand(3).getImm(); - DebugLoc dl = MI->getDebugLoc(); + unsigned dest = MI.getOperand(0).getReg(); + unsigned src = MI.getOperand(1).getReg(); + unsigned SizeVal = MI.getOperand(2).getImm(); + unsigned Align = MI.getOperand(3).getImm(); + DebugLoc dl = MI.getDebugLoc(); MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -7973,7 +7974,7 @@ srcIn = srcOut; destIn = destOut; } - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return BB; } @@ -8117,16 +8118,16 @@ destIn = destOut; } - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return BB; } MachineBasicBlock * -ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI, +ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, MachineBasicBlock *MBB) const { const TargetMachine &TM = getTargetMachine(); const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); assert(Subtarget->isTargetWindows() && "__chkstk is only supported on Windows"); @@ -8185,14 +8186,14 @@ .addReg(ARM::R4, RegState::Kill) .setMIFlags(MachineInstr::FrameSetup))); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } MachineBasicBlock * -ARMTargetLowering::EmitLowered__dbzchk(MachineInstr *MI, +ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI, MachineBasicBlock *MBB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); const TargetInstrInfo *TII = Subtarget->getInstrInfo(); @@ -8208,76 +8209,76 @@ MBB->addSuccessor(TrapBB); BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ)) - .addReg(MI->getOperand(0).getReg()) + .addReg(MI.getOperand(0).getReg()) .addMBB(TrapBB); AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::t2B)).addMBB(ContBB)); MBB->addSuccessor(ContBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return ContBB; } MachineBasicBlock * -ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget->getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); bool isThumb2 = Subtarget->isThumb2(); - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: { - MI->dump(); + MI.dump(); llvm_unreachable("Unexpected instr type to insert"); } // The Thumb2 pre-indexed stores have the same MI operands, they just // define them differently in the .td files from the isel patterns, so // they need pseudos. case ARM::t2STR_preidx: - MI->setDesc(TII->get(ARM::t2STR_PRE)); + MI.setDesc(TII->get(ARM::t2STR_PRE)); return BB; case ARM::t2STRB_preidx: - MI->setDesc(TII->get(ARM::t2STRB_PRE)); + MI.setDesc(TII->get(ARM::t2STRB_PRE)); return BB; case ARM::t2STRH_preidx: - MI->setDesc(TII->get(ARM::t2STRH_PRE)); + MI.setDesc(TII->get(ARM::t2STRH_PRE)); return BB; case ARM::STRi_preidx: case ARM::STRBi_preidx: { - unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? - ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; + unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM + : ARM::STRB_PRE_IMM; // Decode the offset. - unsigned Offset = MI->getOperand(4).getImm(); + unsigned Offset = MI.getOperand(4).getImm(); bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; Offset = ARM_AM::getAM2Offset(Offset); if (isSub) Offset = -Offset; - MachineMemOperand *MMO = *MI->memoperands_begin(); + MachineMemOperand *MMO = *MI.memoperands_begin(); BuildMI(*BB, MI, dl, TII->get(NewOpc)) - .addOperand(MI->getOperand(0)) // Rn_wb - .addOperand(MI->getOperand(1)) // Rt - .addOperand(MI->getOperand(2)) // Rn - .addImm(Offset) // offset (skip GPR==zero_reg) - .addOperand(MI->getOperand(5)) // pred - .addOperand(MI->getOperand(6)) - .addMemOperand(MMO); - MI->eraseFromParent(); + .addOperand(MI.getOperand(0)) // Rn_wb + .addOperand(MI.getOperand(1)) // Rt + .addOperand(MI.getOperand(2)) // Rn + .addImm(Offset) // offset (skip GPR==zero_reg) + .addOperand(MI.getOperand(5)) // pred + .addOperand(MI.getOperand(6)) + .addMemOperand(MMO); + MI.eraseFromParent(); return BB; } case ARM::STRr_preidx: case ARM::STRBr_preidx: case ARM::STRH_preidx: { unsigned NewOpc; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("unexpected opcode!"); case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; } MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); - for (unsigned i = 0; i < MI->getNumOperands(); ++i) - MIB.addOperand(MI->getOperand(i)); - MI->eraseFromParent(); + for (unsigned i = 0; i < MI.getNumOperands(); ++i) + MIB.addOperand(MI.getOperand(i)); + MI.eraseFromParent(); return BB; } @@ -8310,8 +8311,10 @@ BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) - .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); + BuildMI(BB, dl, TII->get(ARM::tBcc)) + .addMBB(sinkMBB) + .addImm(MI.getOperand(3).getImm()) + .addReg(MI.getOperand(4).getReg()); // copy0MBB: // %FalseValue = ... @@ -8325,12 +8328,13 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII->get(ARM::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) - .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); + BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(1).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -8341,10 +8345,10 @@ // Compare both parts that make up the double comparison separately for // equality. - bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; + bool RHSisZero = MI.getOpcode() == ARM::BCCZi64; - unsigned LHS1 = MI->getOperand(1).getReg(); - unsigned LHS2 = MI->getOperand(2).getReg(); + unsigned LHS1 = MI.getOperand(1).getReg(); + unsigned LHS2 = MI.getOperand(2).getReg(); if (RHSisZero) { AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) @@ -8353,8 +8357,8 @@ .addReg(LHS2).addImm(0) .addImm(ARMCC::EQ).addReg(ARM::CPSR); } else { - unsigned RHS1 = MI->getOperand(3).getReg(); - unsigned RHS2 = MI->getOperand(4).getReg(); + unsigned RHS1 = MI.getOperand(3).getReg(); + unsigned RHS2 = MI.getOperand(4).getReg(); AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) .addReg(LHS1).addReg(RHS1)); @@ -8363,9 +8367,9 @@ .addImm(ARMCC::EQ).addReg(ARM::CPSR); } - MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); + MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB(); MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); - if (MI->getOperand(0).getImm() == ARMCC::NE) + if (MI.getOperand(0).getImm() == ARMCC::NE) std::swap(destMBB, exitMBB); BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) @@ -8375,7 +8379,7 @@ else BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -8412,9 +8416,9 @@ Fn->insert(BBI, RSBBB); Fn->insert(BBI, SinkBB); - unsigned int ABSSrcReg = MI->getOperand(1).getReg(); - unsigned int ABSDstReg = MI->getOperand(0).getReg(); - bool ABSSrcKIll = MI->getOperand(1).isKill(); + unsigned int ABSSrcReg = MI.getOperand(1).getReg(); + unsigned int ABSDstReg = MI.getOperand(0).getReg(); + bool ABSSrcKIll = MI.getOperand(1).isKill(); bool isThumb2 = Subtarget->isThumb2(); MachineRegisterInfo &MRI = Fn->getRegInfo(); // In Thumb mode S must not be specified if source register is the SP or @@ -8459,7 +8463,7 @@ .addReg(ABSSrcReg).addMBB(BB); // remove ABS instruction - MI->eraseFromParent(); + MI.eraseFromParent(); // return last added BB return SinkBB; @@ -8478,38 +8482,38 @@ /// when it is expanded into LDM/STM. This is done as a post-isel lowering /// instead of as a custom inserter because we need the use list from the SDNode. static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, - MachineInstr *MI, const SDNode *Node) { + MachineInstr &MI, const SDNode *Node) { bool isThumb1 = Subtarget->isThumb1Only(); - DebugLoc DL = MI->getDebugLoc(); - MachineFunction *MF = MI->getParent()->getParent(); + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MI.getParent()->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); MachineInstrBuilder MIB(*MF, MI); // If the new dst/src is unused mark it as dead. if (!Node->hasAnyUseOfValue(0)) { - MI->getOperand(0).setIsDead(true); + MI.getOperand(0).setIsDead(true); } if (!Node->hasAnyUseOfValue(1)) { - MI->getOperand(1).setIsDead(true); + MI.getOperand(1).setIsDead(true); } // The MEMCPY both defines and kills the scratch registers. - for (unsigned I = 0; I != MI->getOperand(4).getImm(); ++I) { + for (unsigned I = 0; I != MI.getOperand(4).getImm(); ++I) { unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass : &ARM::GPRRegClass); MIB.addReg(TmpReg, RegState::Define|RegState::Dead); } } -void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, +void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { - if (MI->getOpcode() == ARM::MEMCPY) { + if (MI.getOpcode() == ARM::MEMCPY) { attachMEMCPYScratchRegs(Subtarget, MI, Node); return; } - const MCInstrDesc *MCID = &MI->getDesc(); + const MCInstrDesc *MCID = &MI.getDesc(); // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, // RSC. Coming out of isel, they have an implicit CPSR def, but the optional // operand is still set to noreg. If needed, set the optional operand's @@ -8518,24 +8522,24 @@ // e.g. ADCS (..., CPSR) -> ADC (... opt:CPSR). // Rename pseudo opcodes. - unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); + unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode()); if (NewOpc) { const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo(); MCID = &TII->get(NewOpc); - assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 && + assert(MCID->getNumOperands() == MI.getDesc().getNumOperands() + 1 && "converted opcode should be the same except for cc_out"); - MI->setDesc(*MCID); + MI.setDesc(*MCID); // Add the optional cc_out operand - MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); + MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); } unsigned ccOutIdx = MCID->getNumOperands() - 1; // Any ARM instruction that sets the 's' bit should specify an optional // "cc_out" operand in the last operand position. - if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { + if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { assert(!NewOpc && "Optional cc_out operand required"); return; } @@ -8543,14 +8547,14 @@ // since we already have an optional CPSR def. bool definesCPSR = false; bool deadCPSR = false; - for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands(); - i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (unsigned i = MCID->getNumOperands(), e = MI.getNumOperands(); i != e; + ++i) { + const MachineOperand &MO = MI.getOperand(i); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { definesCPSR = true; if (MO.isDead()) deadCPSR = true; - MI->RemoveOperand(i); + MI.RemoveOperand(i); break; } } @@ -8560,14 +8564,14 @@ } assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); if (deadCPSR) { - assert(!MI->getOperand(ccOutIdx).getReg() && + assert(!MI.getOperand(ccOutIdx).getReg() && "expect uninitialized optional cc_out operand"); return; } // If this instruction was defined with an optional CPSR def and its dag node // had a live implicit CPSR def, then activate the optional CPSR def. - MachineOperand &MO = MI->getOperand(ccOutIdx); + MachineOperand &MO = MI.getOperand(ccOutIdx); MO.setReg(ARM::CPSR); MO.setIsDef(true); } Index: lib/Target/AVR/AVRISelLowering.h =================================================================== --- lib/Target/AVR/AVRISelLowering.h +++ lib/Target/AVR/AVRISelLowering.h @@ -93,7 +93,7 @@ bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; ConstraintType getConstraintType(StringRef Constraint) const override; Index: lib/Target/BPF/BPFISelLowering.h =================================================================== --- lib/Target/BPF/BPFISelLowering.h +++ lib/Target/BPF/BPFISelLowering.h @@ -43,7 +43,7 @@ const char *getTargetNodeName(unsigned Opcode) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; private: Index: lib/Target/BPF/BPFISelLowering.cpp =================================================================== --- lib/Target/BPF/BPFISelLowering.cpp +++ lib/Target/BPF/BPFISelLowering.cpp @@ -493,12 +493,12 @@ } MachineBasicBlock * -BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert"); + assert(MI.getOpcode() == BPF::Select && "Unexpected instr type to insert"); // To "insert" a SELECT instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg @@ -529,9 +529,9 @@ BB->addSuccessor(Copy1MBB); // Insert Branch if Flag - unsigned LHS = MI->getOperand(1).getReg(); - unsigned RHS = MI->getOperand(2).getReg(); - int CC = MI->getOperand(3).getImm(); + unsigned LHS = MI.getOperand(1).getReg(); + unsigned RHS = MI.getOperand(2).getReg(); + int CC = MI.getOperand(3).getImm(); switch (CC) { case ISD::SETGT: BuildMI(BB, DL, TII.get(BPF::JSGT_rr)) @@ -585,12 +585,12 @@ // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] // ... BB = Copy1MBB; - BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(5).getReg()) + BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(5).getReg()) .addMBB(Copy0MBB) - .addReg(MI->getOperand(4).getReg()) + .addReg(MI.getOperand(4).getReg()) .addMBB(ThisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/Hexagon/HexagonISelLowering.h =================================================================== --- lib/Target/Hexagon/HexagonISelLowering.h +++ lib/Target/Hexagon/HexagonISelLowering.h @@ -174,8 +174,9 @@ const SDLoc &dl, SelectionDAG &DAG) const override; bool mayBeEmittedAsTailCall(CallInst *CI) const override; - MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const override; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. Index: lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonISelLowering.cpp +++ lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2813,18 +2813,17 @@ return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T); } -MachineBasicBlock * -HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) - const { - switch (MI->getOpcode()) { - case Hexagon::ALLOCA: { - MachineFunction *MF = BB->getParent(); - auto *FuncInfo = MF->getInfo(); - FuncInfo->addAllocaAdjustInst(MI); - return BB; - } - default: llvm_unreachable("Unexpected instr type to insert"); +MachineBasicBlock *HexagonTargetLowering::EmitInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { + case Hexagon::ALLOCA: { + MachineFunction *MF = BB->getParent(); + auto *FuncInfo = MF->getInfo(); + FuncInfo->addAllocaAdjustInst(&MI); + return BB; + } + default: + llvm_unreachable("Unexpected instr type to insert"); } // switch } Index: lib/Target/MSP430/MSP430ISelLowering.h =================================================================== --- lib/Target/MSP430/MSP430ISelLowering.h +++ lib/Target/MSP430/MSP430ISelLowering.h @@ -121,9 +121,10 @@ bool isZExtFree(EVT VT1, EVT VT2) const override; bool isZExtFree(SDValue Val, EVT VT2) const override; - MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const override; - MachineBasicBlock* EmitShiftInstr(MachineInstr *MI, + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; + MachineBasicBlock *EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const; private: Index: lib/Target/MSP430/MSP430ISelLowering.cpp =================================================================== --- lib/Target/MSP430/MSP430ISelLowering.cpp +++ lib/Target/MSP430/MSP430ISelLowering.cpp @@ -1166,17 +1166,17 @@ // Other Lowering Code //===----------------------------------------------------------------------===// -MachineBasicBlock* -MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, +MachineBasicBlock * +MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const { MachineFunction *F = BB->getParent(); MachineRegisterInfo &RI = F->getRegInfo(); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); unsigned Opc; const TargetRegisterClass * RC; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("Invalid shift opcode!"); case MSP430::Shl8: Opc = MSP430::SHL8r1; @@ -1230,9 +1230,9 @@ unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); unsigned ShiftReg = RI.createVirtualRegister(RC); unsigned ShiftReg2 = RI.createVirtualRegister(RC); - unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); - unsigned SrcReg = MI->getOperand(1).getReg(); - unsigned DstReg = MI->getOperand(0).getReg(); + unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg(); + unsigned SrcReg = MI.getOperand(1).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); // BB: // cmp 0, N @@ -1268,14 +1268,14 @@ .addReg(SrcReg).addMBB(BB) .addReg(ShiftReg2).addMBB(LoopBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return RemBB; } -MachineBasicBlock* -MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +MachineBasicBlock * +MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - unsigned Opc = MI->getOpcode(); + unsigned Opc = MI.getOpcode(); if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || @@ -1283,7 +1283,7 @@ return EmitShiftInstr(MI, BB); const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && "Unexpected instr type to insert"); @@ -1317,8 +1317,8 @@ BB->addSuccessor(copy1MBB); BuildMI(BB, dl, TII.get(MSP430::JCC)) - .addMBB(copy1MBB) - .addImm(MI->getOperand(3).getImm()); + .addMBB(copy1MBB) + .addImm(MI.getOperand(3).getImm()); // copy0MBB: // %FalseValue = ... @@ -1332,11 +1332,12 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = copy1MBB; - BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), - MI->getOperand(0).getReg()) - .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) - .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); + BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/Mips/Mips16ISelLowering.h =================================================================== --- lib/Target/Mips/Mips16ISelLowering.h +++ lib/Target/Mips/Mips16ISelLowering.h @@ -27,7 +27,7 @@ bool *Fast) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; private: @@ -50,32 +50,32 @@ bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const override; - MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI, + MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_T8I8I16_ins( - unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, - MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc, + unsigned CmpiXOpc, bool ImmSigned, + MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_CCRX16_ins( - unsigned SltOpc, - MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_CCRXI16_ins( - unsigned SltiOpc, unsigned SltiXOpc, - MachineInstr *MI, MachineBasicBlock *BB )const; + MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, + MachineInstr &MI, + MachineBasicBlock *BB) const; }; } Index: lib/Target/Mips/Mips16ISelLowering.cpp =================================================================== --- lib/Target/Mips/Mips16ISelLowering.cpp +++ lib/Target/Mips/Mips16ISelLowering.cpp @@ -165,9 +165,9 @@ } MachineBasicBlock * -Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); case Mips::SelBeqZ: @@ -517,12 +517,13 @@ Chain); } -MachineBasicBlock *Mips16TargetLowering:: -emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { +MachineBasicBlock * +Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the @@ -552,8 +553,9 @@ BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) - .addMBB(sinkMBB); + BuildMI(BB, DL, TII->get(Opc)) + .addReg(MI.getOperand(3).getReg()) + .addMBB(sinkMBB); // copy0MBB: // %FalseValue = ... @@ -568,22 +570,23 @@ // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), DL, - TII->get(Mips::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) - .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); + BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * -Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, +Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the @@ -613,8 +616,9 @@ BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) - .addReg(MI->getOperand(4).getReg()); + BuildMI(BB, DL, TII->get(Opc2)) + .addReg(MI.getOperand(3).getReg()) + .addReg(MI.getOperand(4).getReg()); BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); // copy0MBB: @@ -630,24 +634,25 @@ // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), DL, - TII->get(Mips::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) - .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); + BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the @@ -677,8 +682,9 @@ BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) - .addImm(MI->getOperand(4).getImm()); + BuildMI(BB, DL, TII->get(Opc2)) + .addReg(MI.getOperand(3).getReg()) + .addImm(MI.getOperand(4).getImm()); BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); // copy0MBB: @@ -694,42 +700,44 @@ // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), DL, - TII->get(Mips::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) - .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); + BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - unsigned regX = MI->getOperand(0).getReg(); - unsigned regY = MI->getOperand(1).getReg(); - MachineBasicBlock *target = MI->getOperand(2).getMBB(); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) - .addReg(regY); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); - MI->eraseFromParent(); // The pseudo instruction is gone now. + unsigned regX = MI.getOperand(0).getReg(); + unsigned regY = MI.getOperand(1).getReg(); + MachineBasicBlock *target = MI.getOperand(2).getMBB(); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)) + .addReg(regX) + .addReg(regY); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target); + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, - MachineInstr *MI, MachineBasicBlock *BB) const { + MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - unsigned regX = MI->getOperand(0).getReg(); - int64_t imm = MI->getOperand(1).getImm(); - MachineBasicBlock *target = MI->getOperand(2).getMBB(); + unsigned regX = MI.getOperand(0).getReg(); + int64_t imm = MI.getOperand(1).getImm(); + MachineBasicBlock *target = MI.getOperand(2).getMBB(); unsigned CmpOpc; if (isUInt<8>(imm)) CmpOpc = CmpiOpc; @@ -738,10 +746,9 @@ CmpOpc = CmpiXOpc; else llvm_unreachable("immediate field not usable"); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) - .addImm(imm); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); - MI->eraseFromParent(); // The pseudo instruction is gone now. + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target); + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -756,38 +763,38 @@ } MachineBasicBlock * -Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr *MI, +Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - unsigned CC = MI->getOperand(0).getReg(); - unsigned regX = MI->getOperand(1).getReg(); - unsigned regY = MI->getOperand(2).getReg(); - BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg( - regY); - BuildMI(*BB, MI, MI->getDebugLoc(), - TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); - MI->eraseFromParent(); // The pseudo instruction is gone now. + unsigned CC = MI.getOperand(0).getReg(); + unsigned regX = MI.getOperand(1).getReg(); + unsigned regY = MI.getOperand(2).getReg(); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)) + .addReg(regX) + .addReg(regY); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC) + .addReg(Mips::T8); + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, - MachineInstr *MI, + MachineInstr &MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - unsigned CC = MI->getOperand(0).getReg(); - unsigned regX = MI->getOperand(1).getReg(); - int64_t Imm = MI->getOperand(2).getImm(); + unsigned CC = MI.getOperand(0).getReg(); + unsigned regX = MI.getOperand(1).getReg(); + int64_t Imm = MI.getOperand(2).getImm(); unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); - BuildMI(*BB, MI, MI->getDebugLoc(), - TII->get(SltOpc)).addReg(regX).addImm(Imm); - BuildMI(*BB, MI, MI->getDebugLoc(), - TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); - MI->eraseFromParent(); // The pseudo instruction is gone now. + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm); + BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC) + .addReg(Mips::T8); + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/Mips/MipsISelLowering.h =================================================================== --- lib/Target/Mips/MipsISelLowering.h +++ lib/Target/Mips/MipsISelLowering.h @@ -266,7 +266,7 @@ SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; void HandleByVal(CCState *, unsigned &, unsigned) const override; @@ -572,24 +572,28 @@ } /// Emit a sign-extension using sll/sra, seb, or seh appropriately. - MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, + MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, unsigned SrcRec) const; - MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, - unsigned Size, unsigned BinOpcode, bool Nand = false) const; - MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, - MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, - bool Nand = false) const; - MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, - MachineBasicBlock *BB, unsigned Size) const; - MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, - MachineBasicBlock *BB, unsigned Size) const; - MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, - MachineBasicBlock *BB, bool isFPCmp, - unsigned Opc) const; + MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, + unsigned Size, unsigned BinOpcode, + bool Nand = false) const; + MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Size, + unsigned BinOpcode, + bool Nand = false) const; + MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Size) const; + MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Size) const; + MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB, + bool isFPCmp, unsigned Opc) const; }; /// Create MipsTargetLowering objects. Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -935,7 +935,7 @@ return VReg; } -static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI, +static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips) { @@ -945,11 +945,12 @@ // Insert instruction "teq $divisor_reg, $zero, 7". MachineBasicBlock::iterator I(MI); MachineInstrBuilder MIB; - MachineOperand &Divisor = MI->getOperand(2); - MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), + MachineOperand &Divisor = MI.getOperand(2); + MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) - .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) - .addReg(Mips::ZERO).addImm(7); + .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) + .addReg(Mips::ZERO) + .addImm(7); // Use the 32-bit sub-register if this is a 64-bit division. if (Is64Bit) @@ -965,9 +966,9 @@ } MachineBasicBlock * -MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("Unexpected instr type to insert"); case Mips::ATOMIC_LOAD_ADD_I8: @@ -1097,10 +1098,11 @@ // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) -MachineBasicBlock * -MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, - unsigned Size, unsigned BinOpcode, - bool Nand) const { +MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Size, + unsigned BinOpcode, + bool Nand) const { assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); MachineFunction *MF = BB->getParent(); @@ -1108,7 +1110,7 @@ const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const bool ArePtrs64bit = ABI.ArePtrs64bit(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); unsigned LL, SC, AND, NOR, ZERO, BEQ; if (Size == 4) { @@ -1137,9 +1139,9 @@ BEQ = Mips::BEQ64; } - unsigned OldVal = MI->getOperand(0).getReg(); - unsigned Ptr = MI->getOperand(1).getReg(); - unsigned Incr = MI->getOperand(2).getReg(); + unsigned OldVal = MI.getOperand(0).getReg(); + unsigned Ptr = MI.getOperand(1).getReg(); + unsigned Incr = MI.getOperand(2).getReg(); unsigned StoreVal = RegInfo.createVirtualRegister(RC); unsigned AndRes = RegInfo.createVirtualRegister(RC); @@ -1186,16 +1188,16 @@ BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return exitMBB; } MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( - MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, + MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, unsigned SrcReg) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - const DebugLoc &DL = MI->getDebugLoc(); + const DebugLoc &DL = MI.getDebugLoc(); if (Subtarget.hasMips32r2() && Size == 1) { BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); @@ -1222,7 +1224,7 @@ } MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( - MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, + MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, bool Nand) const { assert((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."); @@ -1234,11 +1236,11 @@ const TargetRegisterClass *RCp = getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Ptr = MI->getOperand(1).getReg(); - unsigned Incr = MI->getOperand(2).getReg(); + unsigned Dest = MI.getOperand(0).getReg(); + unsigned Ptr = MI.getOperand(1).getReg(); + unsigned Incr = MI.getOperand(2).getReg(); unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); @@ -1381,14 +1383,14 @@ .addReg(MaskedOldVal1).addReg(ShiftAmt); BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return exitMBB; } -MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, - MachineBasicBlock *BB, - unsigned Size) const { +MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, + MachineBasicBlock *BB, + unsigned Size) const { assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); MachineFunction *MF = BB->getParent(); @@ -1396,7 +1398,7 @@ const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const bool ArePtrs64bit = ABI.ArePtrs64bit(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); unsigned LL, SC, ZERO, BNE, BEQ; if (Size == 4) { @@ -1423,10 +1425,10 @@ BEQ = Mips::BEQ64; } - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Ptr = MI->getOperand(1).getReg(); - unsigned OldVal = MI->getOperand(2).getReg(); - unsigned NewVal = MI->getOperand(3).getReg(); + unsigned Dest = MI.getOperand(0).getReg(); + unsigned Ptr = MI.getOperand(1).getReg(); + unsigned OldVal = MI.getOperand(2).getReg(); + unsigned NewVal = MI.getOperand(3).getReg(); unsigned Success = RegInfo.createVirtualRegister(RC); @@ -1471,15 +1473,13 @@ BuildMI(BB, DL, TII->get(BEQ)) .addReg(Success).addReg(ZERO).addMBB(loop1MBB); - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return exitMBB; } -MachineBasicBlock * -MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, - MachineBasicBlock *BB, - unsigned Size) const { +MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( + MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { assert((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."); @@ -1490,12 +1490,12 @@ const TargetRegisterClass *RCp = getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Ptr = MI->getOperand(1).getReg(); - unsigned CmpVal = MI->getOperand(2).getReg(); - unsigned NewVal = MI->getOperand(3).getReg(); + unsigned Dest = MI.getOperand(0).getReg(); + unsigned Ptr = MI.getOperand(1).getReg(); + unsigned CmpVal = MI.getOperand(2).getReg(); + unsigned NewVal = MI.getOperand(3).getReg(); unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); @@ -1628,21 +1628,21 @@ .addReg(MaskedOldVal0).addReg(ShiftAmt); BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); - MI->eraseFromParent(); // The instruction is gone now. + MI.eraseFromParent(); // The instruction is gone now. return exitMBB; } -MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI, +MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const { MachineFunction *MF = BB->getParent(); const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineBasicBlock::iterator II(MI); - unsigned Fc = MI->getOperand(1).getReg(); + unsigned Fc = MI.getOperand(1).getReg(); const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); @@ -1654,7 +1654,7 @@ // We don't erase the original instruction, we just replace the condition // register with the 64-bit super-register. - MI->getOperand(1).setReg(Fc2); + MI.getOperand(1).setReg(Fc2); return BB; } @@ -3956,16 +3956,17 @@ State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); } -MachineBasicBlock * -MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB, - bool isFPCmp, unsigned Opc) const { +MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, + MachineBasicBlock *BB, + bool isFPCmp, + unsigned Opc) const { assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && "Subtarget already supports SELECT nodes with the use of" "conditional-move instructions."); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // To "insert" a SELECT instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -3999,14 +4000,14 @@ if (isFPCmp) { // bc1[tf] cc, sinkMBB BuildMI(BB, DL, TII->get(Opc)) - .addReg(MI->getOperand(1).getReg()) - .addMBB(sinkMBB); + .addReg(MI.getOperand(1).getReg()) + .addMBB(sinkMBB); } else { // bne rs, $0, sinkMBB BuildMI(BB, DL, TII->get(Opc)) - .addReg(MI->getOperand(1).getReg()) - .addReg(Mips::ZERO) - .addMBB(sinkMBB); + .addReg(MI.getOperand(1).getReg()) + .addReg(Mips::ZERO) + .addMBB(sinkMBB); } // copy0MBB: @@ -4022,12 +4023,13 @@ // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), DL, - TII->get(Mips::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) - .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB); + BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(2).getReg()) + .addMBB(thisMBB) + .addReg(MI.getOperand(3).getReg()) + .addMBB(copy0MBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/Mips/MipsSEISelLowering.h =================================================================== --- lib/Target/Mips/MipsSEISelLowering.h +++ lib/Target/Mips/MipsSEISelLowering.h @@ -40,7 +40,7 @@ SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; bool isShuffleMaskLegal(const SmallVectorImpl &Mask, @@ -77,39 +77,39 @@ /// depending on the indices in the shuffle. SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; - MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, + MachineBasicBlock *emitBPOSGE32(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, + MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const; /// \brief Emit the COPY_FW pseudo instruction - MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, + MachineBasicBlock *emitCOPY_FW(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the COPY_FD pseudo instruction - MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, + MachineBasicBlock *emitCOPY_FD(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the INSERT_FW pseudo instruction - MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, + MachineBasicBlock *emitINSERT_FW(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the INSERT_FD pseudo instruction - MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, + MachineBasicBlock *emitINSERT_FD(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction - MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, + MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes, bool IsFP) const; /// \brief Emit the FILL_FW pseudo instruction - MachineBasicBlock *emitFILL_FW(MachineInstr *MI, + MachineBasicBlock *emitFILL_FW(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the FILL_FD pseudo instruction - MachineBasicBlock *emitFILL_FD(MachineInstr *MI, + MachineBasicBlock *emitFILL_FD(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the FEXP2_W_1 pseudo instructions. - MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, + MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI, MachineBasicBlock *BB) const; /// \brief Emit the FEXP2_D_1 pseudo instructions. - MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, + MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI, MachineBasicBlock *BB) const; }; } Index: lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEISelLowering.cpp +++ lib/Target/Mips/MipsSEISelLowering.cpp @@ -1111,9 +1111,9 @@ } MachineBasicBlock * -MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); case Mips::BPOSGE32_PSEUDO: @@ -2904,8 +2904,9 @@ return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); } -MachineBasicBlock * MipsSETargetLowering:: -emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ +MachineBasicBlock * +MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI, + MachineBasicBlock *BB) const { // $bb: // bposge32_pseudo $vr0 // => @@ -2922,7 +2923,7 @@ MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const TargetRegisterClass *RC = &Mips::GPR32RegClass; - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = std::next(MachineFunction::iterator(BB)); MachineFunction *F = BB->getParent(); @@ -2962,16 +2963,18 @@ // Insert phi function to $Sink. BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), - MI->getOperand(0).getReg()) - .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); + MI.getOperand(0).getReg()) + .addReg(VR2) + .addMBB(FBB) + .addReg(VR1) + .addMBB(TBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return Sink; } -MachineBasicBlock * MipsSETargetLowering:: -emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, - unsigned BranchOp) const{ +MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo( + MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const { // $bb: // vany_nonzero $rd, $ws // => @@ -2989,7 +2992,7 @@ MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const TargetRegisterClass *RC = &Mips::GPR32RegClass; - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = std::next(MachineFunction::iterator(BB)); MachineFunction *F = BB->getParent(); @@ -3013,8 +3016,8 @@ // Insert the real bnz.b instruction to $BB. BuildMI(BB, DL, TII->get(BranchOp)) - .addReg(MI->getOperand(1).getReg()) - .addMBB(TBB); + .addReg(MI.getOperand(1).getReg()) + .addMBB(TBB); // Fill $FBB. unsigned RD1 = RegInfo.createVirtualRegister(RC); @@ -3029,10 +3032,13 @@ // Insert phi function to $Sink. BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), - MI->getOperand(0).getReg()) - .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); + MI.getOperand(0).getReg()) + .addReg(RD1) + .addMBB(FBB) + .addReg(RD2) + .addMBB(TBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return Sink; } @@ -3046,14 +3052,15 @@ // When n is zero, the equivalent operation can be performed with (potentially) // zero instructions due to register overlaps. This optimization is never valid // for lane 1 because it would require FR=0 mode which isn't supported by MSA. -MachineBasicBlock * MipsSETargetLowering:: -emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ +MachineBasicBlock * +MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI, + MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Fd = MI->getOperand(0).getReg(); - unsigned Ws = MI->getOperand(1).getReg(); - unsigned Lane = MI->getOperand(2).getImm(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Fd = MI.getOperand(0).getReg(); + unsigned Ws = MI.getOperand(1).getReg(); + unsigned Lane = MI.getOperand(2).getImm(); if (Lane == 0) { unsigned Wt = Ws; @@ -3075,7 +3082,7 @@ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3089,16 +3096,17 @@ // When n is zero, the equivalent operation can be performed with (potentially) // zero instructions due to register overlaps. This optimization is always // valid because FR=1 mode which is the only supported mode in MSA. -MachineBasicBlock * MipsSETargetLowering:: -emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ +MachineBasicBlock * +MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI, + MachineBasicBlock *BB) const { assert(Subtarget.isFP64bit()); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - unsigned Fd = MI->getOperand(0).getReg(); - unsigned Ws = MI->getOperand(1).getReg(); - unsigned Lane = MI->getOperand(2).getImm() * 2; - DebugLoc DL = MI->getDebugLoc(); + unsigned Fd = MI.getOperand(0).getReg(); + unsigned Ws = MI.getOperand(1).getReg(); + unsigned Lane = MI.getOperand(2).getImm() * 2; + DebugLoc DL = MI.getDebugLoc(); if (Lane == 0) BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); @@ -3109,7 +3117,7 @@ BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3120,15 +3128,15 @@ // subreg_to_reg $wt:sub_lo, $fs // insve_w $wd[$n], $wd_in, $wt[0] MachineBasicBlock * -MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, +MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Wd = MI->getOperand(0).getReg(); - unsigned Wd_in = MI->getOperand(1).getReg(); - unsigned Lane = MI->getOperand(2).getImm(); - unsigned Fs = MI->getOperand(3).getReg(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned Wd_in = MI.getOperand(1).getReg(); + unsigned Lane = MI.getOperand(2).getImm(); + unsigned Fs = MI.getOperand(3).getReg(); unsigned Wt = RegInfo.createVirtualRegister( Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : &Mips::MSA128WEvensRegClass); @@ -3143,7 +3151,7 @@ .addReg(Wt) .addImm(0); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3154,17 +3162,17 @@ // subreg_to_reg $wt:sub_64, $fs // insve_d $wd[$n], $wd_in, $wt[0] MachineBasicBlock * -MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, +MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI, MachineBasicBlock *BB) const { assert(Subtarget.isFP64bit()); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Wd = MI->getOperand(0).getReg(); - unsigned Wd_in = MI->getOperand(1).getReg(); - unsigned Lane = MI->getOperand(2).getImm(); - unsigned Fs = MI->getOperand(3).getReg(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned Wd_in = MI.getOperand(1).getReg(); + unsigned Lane = MI.getOperand(2).getImm(); + unsigned Fs = MI.getOperand(3).getReg(); unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) @@ -3177,7 +3185,7 @@ .addReg(Wt) .addImm(0); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3201,18 +3209,16 @@ // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0) // (NEG $lanetmp2, $lanetmp1) // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2) -MachineBasicBlock * -MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI, - MachineBasicBlock *BB, - unsigned EltSizeInBytes, - bool IsFP) const { +MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX( + MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes, + bool IsFP) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Wd = MI->getOperand(0).getReg(); - unsigned SrcVecReg = MI->getOperand(1).getReg(); - unsigned LaneReg = MI->getOperand(2).getReg(); - unsigned SrcValReg = MI->getOperand(3).getReg(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned SrcVecReg = MI.getOperand(1).getReg(); + unsigned LaneReg = MI.getOperand(2).getReg(); + unsigned SrcValReg = MI.getOperand(3).getReg(); const TargetRegisterClass *VecRC = nullptr; // FIXME: This should be true for N32 too. @@ -3306,7 +3312,7 @@ .addReg(WdTmp2) .addReg(LaneTmp2, 0, SubRegIdx); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3318,13 +3324,13 @@ // insert_subreg $wt2:subreg_lo, $wt1, $fs // splati.w $wd, $wt2[0] MachineBasicBlock * -MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, +MipsSETargetLowering::emitFILL_FW(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Wd = MI->getOperand(0).getReg(); - unsigned Fs = MI->getOperand(1).getReg(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned Fs = MI.getOperand(1).getReg(); unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); @@ -3335,7 +3341,7 @@ .addImm(Mips::sub_lo); BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3347,15 +3353,15 @@ // insert_subreg $wt2:subreg_64, $wt1, $fs // splati.d $wd, $wt2[0] MachineBasicBlock * -MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, +MipsSETargetLowering::emitFILL_FD(MachineInstr &MI, MachineBasicBlock *BB) const { assert(Subtarget.isFP64bit()); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); - unsigned Wd = MI->getOperand(0).getReg(); - unsigned Fs = MI->getOperand(1).getReg(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned Fs = MI.getOperand(1).getReg(); unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); @@ -3366,7 +3372,7 @@ .addImm(Mips::sub_64); BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3377,25 +3383,25 @@ // ldi.w $ws, 1 // fexp2.w $wd, $ws, $wt MachineBasicBlock * -MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, +MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetRegisterClass *RC = &Mips::MSA128WRegClass; unsigned Ws1 = RegInfo.createVirtualRegister(RC); unsigned Ws2 = RegInfo.createVirtualRegister(RC); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // Splat 1.0 into a vector BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); // Emit 1.0 * fexp2(Wt) - BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) + BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg()) .addReg(Ws2) - .addReg(MI->getOperand(1).getReg()); + .addReg(MI.getOperand(1).getReg()); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -3406,24 +3412,24 @@ // ldi.d $ws, 1 // fexp2.d $wd, $ws, $wt MachineBasicBlock * -MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, +MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetRegisterClass *RC = &Mips::MSA128DRegClass; unsigned Ws1 = RegInfo.createVirtualRegister(RC); unsigned Ws2 = RegInfo.createVirtualRegister(RC); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // Splat 1.0 into a vector BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); // Emit 1.0 * fexp2(Wt) - BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) + BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg()) .addReg(Ws2) - .addReg(MI->getOperand(1).getReg()); + .addReg(MI.getOperand(1).getReg()); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h +++ lib/Target/PowerPC/PPCISelLowering.h @@ -534,20 +534,21 @@ bool IsStore, bool IsLoad) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *MBB) const override; - MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; + MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode) const; - MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, + MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, - bool is8bit, unsigned Opcode) const; + bool is8bit, + unsigned Opcode) const; - MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; ConstraintType getConstraintType(StringRef Constraint) const override; Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -8307,7 +8307,7 @@ } MachineBasicBlock * -PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, +PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, unsigned AtomicSize, unsigned BinOpcode) const { // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. @@ -8342,11 +8342,11 @@ MachineFunction *F = BB->getParent(); MachineFunction::iterator It = ++BB->getIterator(); - unsigned dest = MI->getOperand(0).getReg(); - unsigned ptrA = MI->getOperand(1).getReg(); - unsigned ptrB = MI->getOperand(2).getReg(); - unsigned incr = MI->getOperand(3).getReg(); - DebugLoc dl = MI->getDebugLoc(); + unsigned dest = MI.getOperand(0).getReg(); + unsigned ptrA = MI.getOperand(1).getReg(); + unsigned ptrB = MI.getOperand(2).getReg(); + unsigned incr = MI.getOperand(3).getReg(); + DebugLoc dl = MI.getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -8391,9 +8391,9 @@ } MachineBasicBlock * -PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, +PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, - bool is8bit, // operation + bool is8bit, // operation unsigned BinOpcode) const { // If we support part-word atomic mnemonics, just use them if (Subtarget.hasPartwordAtomics()) @@ -8412,11 +8412,11 @@ MachineFunction *F = BB->getParent(); MachineFunction::iterator It = ++BB->getIterator(); - unsigned dest = MI->getOperand(0).getReg(); - unsigned ptrA = MI->getOperand(1).getReg(); - unsigned ptrB = MI->getOperand(2).getReg(); - unsigned incr = MI->getOperand(3).getReg(); - DebugLoc dl = MI->getDebugLoc(); + unsigned dest = MI.getOperand(0).getReg(); + unsigned ptrA = MI.getOperand(1).getReg(); + unsigned ptrB = MI.getOperand(2).getReg(); + unsigned incr = MI.getOperand(3).getReg(); + DebugLoc dl = MI.getDebugLoc(); MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -8522,10 +8522,10 @@ return BB; } -llvm::MachineBasicBlock* -PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, +llvm::MachineBasicBlock * +PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineFunction *MF = MBB->getParent(); @@ -8535,10 +8535,10 @@ MachineFunction::iterator I = ++MBB->getIterator(); // Memory Reference - MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); - MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin(); + MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end(); - unsigned DstReg = MI->getOperand(0).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); const TargetRegisterClass *RC = MRI.getRegClass(DstReg); assert(RC->hasType(MVT::i32) && "Invalid destination!"); unsigned mainDstReg = MRI.createVirtualRegister(RC); @@ -8595,7 +8595,7 @@ // Prepare IP either in reg. const TargetRegisterClass *PtrRC = getRegClassFor(PVT); unsigned LabelReg = MRI.createVirtualRegister(PtrRC); - unsigned BufReg = MI->getOperand(1).getReg(); + unsigned BufReg = MI.getOperand(1).getReg(); if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) { setUsesTOCBasePtr(*MBB->getParent()); @@ -8665,22 +8665,22 @@ .addReg(mainDstReg).addMBB(mainMBB) .addReg(restoreDstReg).addMBB(thisMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return sinkMBB; } MachineBasicBlock * -PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, +PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineFunction *MF = MBB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); // Memory Reference - MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); - MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin(); + MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end(); MVT PVT = getPointerTy(MF->getDataLayout()); assert((PVT == MVT::i64 || PVT == MVT::i32) && @@ -8705,7 +8705,7 @@ const int64_t TOCOffset = 3 * PVT.getStoreSize(); const int64_t BPOffset = 4 * PVT.getStoreSize(); - unsigned BufReg = MI->getOperand(0).getReg(); + unsigned BufReg = MI.getOperand(0).getReg(); // Reload FP (the jumped-to function may not have had a // frame pointer, and if so, then its r31 will be restored @@ -8772,34 +8772,34 @@ TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } MachineBasicBlock * -PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - if (MI->getOpcode() == TargetOpcode::STACKMAP || - MI->getOpcode() == TargetOpcode::PATCHPOINT) { + if (MI.getOpcode() == TargetOpcode::STACKMAP || + MI.getOpcode() == TargetOpcode::PATCHPOINT) { if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() && - MI->getOpcode() == TargetOpcode::PATCHPOINT) { + MI.getOpcode() == TargetOpcode::PATCHPOINT) { // Call lowering should have added an r2 operand to indicate a dependence // on the TOC base pointer value. It can't however, because there is no // way to mark the dependence as implicit there, and so the stackmap code // will confuse it with a regular operand. Instead, add the dependence // here. setUsesTOCBasePtr(*BB->getParent()); - MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true)); + MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true)); } return emitPatchPoint(MI, BB); } - if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 || - MI->getOpcode() == PPC::EH_SjLj_SetJmp64) { + if (MI.getOpcode() == PPC::EH_SjLj_SetJmp32 || + MI.getOpcode() == PPC::EH_SjLj_SetJmp64) { return emitEHSjLjSetJmp(MI, BB); - } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 || - MI->getOpcode() == PPC::EH_SjLj_LongJmp64) { + } else if (MI.getOpcode() == PPC::EH_SjLj_LongJmp32 || + MI.getOpcode() == PPC::EH_SjLj_LongJmp64) { return emitEHSjLjLongJmp(MI, BB); } @@ -8812,44 +8812,43 @@ MachineFunction *F = BB->getParent(); - if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || - MI->getOpcode() == PPC::SELECT_CC_I8 || - MI->getOpcode() == PPC::SELECT_I4 || - MI->getOpcode() == PPC::SELECT_I8)) { + if (Subtarget.hasISEL() && + (MI.getOpcode() == PPC::SELECT_CC_I4 || + MI.getOpcode() == PPC::SELECT_CC_I8 || + MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8)) { SmallVector Cond; - if (MI->getOpcode() == PPC::SELECT_CC_I4 || - MI->getOpcode() == PPC::SELECT_CC_I8) - Cond.push_back(MI->getOperand(4)); + if (MI.getOpcode() == PPC::SELECT_CC_I4 || + MI.getOpcode() == PPC::SELECT_CC_I8) + Cond.push_back(MI.getOperand(4)); else Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); - Cond.push_back(MI->getOperand(1)); - - DebugLoc dl = MI->getDebugLoc(); - TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), - Cond, MI->getOperand(2).getReg(), - MI->getOperand(3).getReg()); - } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || - MI->getOpcode() == PPC::SELECT_CC_I8 || - MI->getOpcode() == PPC::SELECT_CC_F4 || - MI->getOpcode() == PPC::SELECT_CC_F8 || - MI->getOpcode() == PPC::SELECT_CC_QFRC || - MI->getOpcode() == PPC::SELECT_CC_QSRC || - MI->getOpcode() == PPC::SELECT_CC_QBRC || - MI->getOpcode() == PPC::SELECT_CC_VRRC || - MI->getOpcode() == PPC::SELECT_CC_VSFRC || - MI->getOpcode() == PPC::SELECT_CC_VSSRC || - MI->getOpcode() == PPC::SELECT_CC_VSRC || - MI->getOpcode() == PPC::SELECT_I4 || - MI->getOpcode() == PPC::SELECT_I8 || - MI->getOpcode() == PPC::SELECT_F4 || - MI->getOpcode() == PPC::SELECT_F8 || - MI->getOpcode() == PPC::SELECT_QFRC || - MI->getOpcode() == PPC::SELECT_QSRC || - MI->getOpcode() == PPC::SELECT_QBRC || - MI->getOpcode() == PPC::SELECT_VRRC || - MI->getOpcode() == PPC::SELECT_VSFRC || - MI->getOpcode() == PPC::SELECT_VSSRC || - MI->getOpcode() == PPC::SELECT_VSRC) { + Cond.push_back(MI.getOperand(1)); + + DebugLoc dl = MI.getDebugLoc(); + TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond, + MI.getOperand(2).getReg(), MI.getOperand(3).getReg()); + } else if (MI.getOpcode() == PPC::SELECT_CC_I4 || + MI.getOpcode() == PPC::SELECT_CC_I8 || + MI.getOpcode() == PPC::SELECT_CC_F4 || + MI.getOpcode() == PPC::SELECT_CC_F8 || + MI.getOpcode() == PPC::SELECT_CC_QFRC || + MI.getOpcode() == PPC::SELECT_CC_QSRC || + MI.getOpcode() == PPC::SELECT_CC_QBRC || + MI.getOpcode() == PPC::SELECT_CC_VRRC || + MI.getOpcode() == PPC::SELECT_CC_VSFRC || + MI.getOpcode() == PPC::SELECT_CC_VSSRC || + MI.getOpcode() == PPC::SELECT_CC_VSRC || + MI.getOpcode() == PPC::SELECT_I4 || + MI.getOpcode() == PPC::SELECT_I8 || + MI.getOpcode() == PPC::SELECT_F4 || + MI.getOpcode() == PPC::SELECT_F8 || + MI.getOpcode() == PPC::SELECT_QFRC || + MI.getOpcode() == PPC::SELECT_QSRC || + MI.getOpcode() == PPC::SELECT_QBRC || + MI.getOpcode() == PPC::SELECT_VRRC || + MI.getOpcode() == PPC::SELECT_VSFRC || + MI.getOpcode() == PPC::SELECT_VSSRC || + MI.getOpcode() == PPC::SELECT_VSRC) { // The incoming instruction knows the destination vreg to set, the // condition code register to branch on, the true/false values to // select between, and a branch opcode to use. @@ -8863,7 +8862,7 @@ MachineBasicBlock *thisMBB = BB; MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); F->insert(It, copy0MBB); F->insert(It, sinkMBB); @@ -8876,23 +8875,24 @@ BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - if (MI->getOpcode() == PPC::SELECT_I4 || - MI->getOpcode() == PPC::SELECT_I8 || - MI->getOpcode() == PPC::SELECT_F4 || - MI->getOpcode() == PPC::SELECT_F8 || - MI->getOpcode() == PPC::SELECT_QFRC || - MI->getOpcode() == PPC::SELECT_QSRC || - MI->getOpcode() == PPC::SELECT_QBRC || - MI->getOpcode() == PPC::SELECT_VRRC || - MI->getOpcode() == PPC::SELECT_VSFRC || - MI->getOpcode() == PPC::SELECT_VSSRC || - MI->getOpcode() == PPC::SELECT_VSRC) { + if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 || + MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 || + MI.getOpcode() == PPC::SELECT_QFRC || + MI.getOpcode() == PPC::SELECT_QSRC || + MI.getOpcode() == PPC::SELECT_QBRC || + MI.getOpcode() == PPC::SELECT_VRRC || + MI.getOpcode() == PPC::SELECT_VSFRC || + MI.getOpcode() == PPC::SELECT_VSSRC || + MI.getOpcode() == PPC::SELECT_VSRC) { BuildMI(BB, dl, TII->get(PPC::BC)) - .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); + .addReg(MI.getOperand(1).getReg()) + .addMBB(sinkMBB); } else { - unsigned SelectPred = MI->getOperand(4).getImm(); + unsigned SelectPred = MI.getOperand(4).getImm(); BuildMI(BB, dl, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); + .addImm(SelectPred) + .addReg(MI.getOperand(1).getReg()) + .addMBB(sinkMBB); } // copy0MBB: @@ -8907,11 +8907,12 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII->get(PPC::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) - .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - } else if (MI->getOpcode() == PPC::ReadTB) { + BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(3).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(thisMBB); + } else if (MI.getOpcode() == PPC::ReadTB) { // To read the 64-bit time-base register on a 32-bit target, we read the // two halves. Should the counter have wrapped while it was being read, we // need to try again. @@ -8926,7 +8927,7 @@ MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); F->insert(It, readMBB); F->insert(It, sinkMBB); @@ -8940,8 +8941,8 @@ MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); - unsigned LoReg = MI->getOperand(0).getReg(); - unsigned HiReg = MI->getOperand(1).getReg(); + unsigned LoReg = MI.getOperand(0).getReg(); + unsigned HiReg = MI.getOperand(1).getReg(); BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); @@ -8956,81 +8957,80 @@ BB->addSuccessor(readMBB); BB->addSuccessor(sinkMBB); - } - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) + } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::AND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::OR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF); - else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) + else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8); - else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) + else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, 0); - else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) + else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16) BB = EmitPartwordAtomicBinary(MI, BB, false, 0); - else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) + else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32) BB = EmitAtomicBinary(MI, BB, 4, 0); - else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) + else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64) BB = EmitAtomicBinary(MI, BB, 8, 0); - else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || - MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 || + else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || + MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 || (Subtarget.hasPartwordAtomics() && - MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) || + MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) || (Subtarget.hasPartwordAtomics() && - MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) { - bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; + MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) { + bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; auto LoadMnemonic = PPC::LDARX; auto StoreMnemonic = PPC::STDCX; - switch(MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("Compare and swap of unknown size"); case PPC::ATOMIC_CMP_SWAP_I8: @@ -9052,12 +9052,12 @@ StoreMnemonic = PPC::STDCX; break; } - unsigned dest = MI->getOperand(0).getReg(); - unsigned ptrA = MI->getOperand(1).getReg(); - unsigned ptrB = MI->getOperand(2).getReg(); - unsigned oldval = MI->getOperand(3).getReg(); - unsigned newval = MI->getOperand(4).getReg(); - DebugLoc dl = MI->getDebugLoc(); + unsigned dest = MI.getOperand(0).getReg(); + unsigned ptrA = MI.getOperand(1).getReg(); + unsigned ptrB = MI.getOperand(2).getReg(); + unsigned oldval = MI.getOperand(3).getReg(); + unsigned newval = MI.getOperand(4).getReg(); + DebugLoc dl = MI.getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -9114,20 +9114,20 @@ // exitMBB: // ... BB = exitMBB; - } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || - MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { + } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || + MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { // We must use 64-bit registers for addresses when targeting 64-bit, // since we're actually doing arithmetic on them. Other registers // can be 32-bit. bool is64bit = Subtarget.isPPC64(); - bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; + bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; - unsigned dest = MI->getOperand(0).getReg(); - unsigned ptrA = MI->getOperand(1).getReg(); - unsigned ptrB = MI->getOperand(2).getReg(); - unsigned oldval = MI->getOperand(3).getReg(); - unsigned newval = MI->getOperand(4).getReg(); - DebugLoc dl = MI->getDebugLoc(); + unsigned dest = MI.getOperand(0).getReg(); + unsigned ptrA = MI.getOperand(1).getReg(); + unsigned ptrB = MI.getOperand(2).getReg(); + unsigned oldval = MI.getOperand(3).getReg(); + unsigned newval = MI.getOperand(4).getReg(); + DebugLoc dl = MI.getDebugLoc(); MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); @@ -9262,14 +9262,14 @@ BB = exitMBB; BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) .addReg(ShiftReg); - } else if (MI->getOpcode() == PPC::FADDrtz) { + } else if (MI.getOpcode() == PPC::FADDrtz) { // This pseudo performs an FADD with rounding mode temporarily forced // to round-to-zero. We emit this via custom inserter since the FPSCR // is not modeled at the SelectionDAG level. - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Src1 = MI->getOperand(1).getReg(); - unsigned Src2 = MI->getOperand(2).getReg(); - DebugLoc dl = MI->getDebugLoc(); + unsigned Dest = MI.getOperand(0).getReg(); + unsigned Src1 = MI.getOperand(1).getReg(); + unsigned Src2 = MI.getOperand(2).getReg(); + DebugLoc dl = MI.getDebugLoc(); MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); @@ -9286,29 +9286,31 @@ // Restore FPSCR value. BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg); - } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT || - MI->getOpcode() == PPC::ANDIo_1_GT_BIT || - MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 || - MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) { - unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 || - MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ? - PPC::ANDIo8 : PPC::ANDIo; - bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT || - MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8); + } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT || + MI.getOpcode() == PPC::ANDIo_1_GT_BIT || + MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 || + MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) { + unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 || + MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) + ? PPC::ANDIo8 + : PPC::ANDIo; + bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT || + MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8); MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass); - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); BuildMI(*BB, MI, dl, TII->get(Opcode), Dest) - .addReg(MI->getOperand(1).getReg()).addImm(1); + .addReg(MI.getOperand(1).getReg()) + .addImm(1); BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), - MI->getOperand(0).getReg()) - .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT); - } else if (MI->getOpcode() == PPC::TCHECK_RET) { - DebugLoc Dl = MI->getDebugLoc(); + MI.getOperand(0).getReg()) + .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT); + } else if (MI.getOpcode() == PPC::TCHECK_RET) { + DebugLoc Dl = MI.getDebugLoc(); MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg); @@ -9317,7 +9319,7 @@ llvm_unreachable("Unexpected instr type to insert"); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } Index: lib/Target/Sparc/SparcISelLowering.h =================================================================== --- lib/Target/Sparc/SparcISelLowering.h +++ lib/Target/Sparc/SparcISelLowering.h @@ -72,8 +72,8 @@ unsigned Depth = 0) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *MBB) const override; + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; const char *getTargetNodeName(unsigned Opcode) const override; @@ -211,11 +211,11 @@ SmallVectorImpl& Results, SelectionDAG &DAG) const override; - MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, + MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const; - MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; }; } // end namespace llvm Index: lib/Target/Sparc/SparcISelLowering.cpp =================================================================== --- lib/Target/Sparc/SparcISelLowering.cpp +++ lib/Target/Sparc/SparcISelLowering.cpp @@ -3092,9 +3092,9 @@ } MachineBasicBlock * -SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("Unknown SELECT_CC!"); case SP::SELECT_CC_Int_ICC: case SP::SELECT_CC_FP_ICC: @@ -3116,13 +3116,12 @@ } } -MachineBasicBlock* -SparcTargetLowering::expandSelectCC(MachineInstr *MI, - MachineBasicBlock *BB, +MachineBasicBlock * +SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const { const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); - unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); + DebugLoc dl = MI.getDebugLoc(); + unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm(); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond // control-flow pattern. The incoming instruction knows the destination vreg @@ -3167,20 +3166,20 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) - .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); + BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } - -MachineBasicBlock* SparcTargetLowering:: -emitEHSjLjLongJmp(MachineInstr *MI, - MachineBasicBlock *MBB) const -{ - DebugLoc DL = MI->getDebugLoc(); +MachineBasicBlock * +SparcTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI, + MachineBasicBlock *MBB) const { + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget->getInstrInfo(); MachineFunction *MF = MBB->getParent(); @@ -3191,7 +3190,7 @@ unsigned RegSize = PVT.getStoreSize(); assert(PVT == MVT::i32 && "Invalid Pointer Size!"); - unsigned Buf = MI->getOperand(0).getReg(); + unsigned Buf = MI.getOperand(0).getReg(); unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass); // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3 @@ -3226,15 +3225,14 @@ // Jump to JmpLoc BuildMI(*MBB, MI, DL, TII->get(SP::JMPLrr)).addReg(SP::G0).addReg(JmpLoc, RegState::Kill).addReg(SP::G0); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } -MachineBasicBlock* SparcTargetLowering:: -emitEHSjLjSetJmp(MachineInstr *MI, - MachineBasicBlock *MBB) const -{ - DebugLoc DL = MI->getDebugLoc(); +MachineBasicBlock * +SparcTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI, + MachineBasicBlock *MBB) const { + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget->getInstrInfo(); MachineFunction *MF = MBB->getParent(); @@ -3245,7 +3243,7 @@ unsigned RegSize = PVT.getStoreSize(); assert(PVT == MVT::i32 && "Invalid Pointer Size!"); - unsigned DstReg = MI->getOperand(0).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); const TargetRegisterClass *RC = MRI.getRegClass(DstReg); assert(RC->hasType(MVT::i32) && "Invalid destination!"); unsigned mainDstReg = MRI.createVirtualRegister(RC); @@ -3292,7 +3290,7 @@ unsigned LabelReg = MRI.createVirtualRegister(&SP::IntRegsRegClass); unsigned LabelReg2 = MRI.createVirtualRegister(&SP::IntRegsRegClass); - unsigned BufReg = MI->getOperand(1).getReg(); + unsigned BufReg = MI.getOperand(1).getReg(); // Instruction to store FP const unsigned FP = SP::I6; @@ -3371,7 +3369,7 @@ .addReg(mainDstReg).addMBB(mainMBB) .addReg(restoreDstReg).addMBB(restoreMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return sinkMBB; } Index: lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.h +++ lib/Target/SystemZ/SystemZISelLowering.h @@ -446,9 +446,9 @@ void insertSSPDeclarations(Module &M) const override { } - MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const - override; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; bool allowTruncateForTailCall(Type *, Type *) const override; bool mayBeEmittedAsTailCall(CallInst *CI) const override; @@ -550,40 +550,33 @@ MachineBasicBlock *Target) const; // Implement EmitInstrWithCustomInserter for individual operation types. - MachineBasicBlock *emitSelect(MachineInstr *MI, - MachineBasicBlock *BB) const; - MachineBasicBlock *emitCondStore(MachineInstr *MI, - MachineBasicBlock *BB, + MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const; - MachineBasicBlock *emitExt128(MachineInstr *MI, - MachineBasicBlock *MBB, + MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, bool ClearEven, unsigned SubReg) const; - MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, + MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, MachineBasicBlock *BB, unsigned BinOpcode, unsigned BitSize, bool Invert = false) const; - MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, + MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode, unsigned KeepOldMask, unsigned BitSize) const; - MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, + MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI, - MachineBasicBlock *BB, + MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode) const; - MachineBasicBlock *emitStringWrapper(MachineInstr *MI, - MachineBasicBlock *BB, + MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode) const; - MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, MachineBasicBlock *MBB, - unsigned Opcode, - bool NoFloat) const; - MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr *MI, + unsigned Opcode, bool NoFloat) const; + MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const; - }; } // end namespace llvm Index: lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.cpp +++ lib/Target/SystemZ/SystemZISelLowering.cpp @@ -5064,7 +5064,7 @@ // Split MBB after MI and return the new block (the one that contains // instructions after MI). -static MachineBasicBlock *splitBlockAfter(MachineInstr *MI, +static MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB) { MachineBasicBlock *NewMBB = emitBlockAfter(MBB); NewMBB->splice(NewMBB->begin(), MBB, @@ -5074,7 +5074,7 @@ } // Split MBB before MI and return the new block (the one that contains MI). -static MachineBasicBlock *splitBlockBefore(MachineInstr *MI, +static MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB) { MachineBasicBlock *NewMBB = emitBlockAfter(MBB); NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end()); @@ -5083,34 +5083,36 @@ } // Force base value Base into a register before MI. Return the register. -static unsigned forceReg(MachineInstr *MI, MachineOperand &Base, +static unsigned forceReg(MachineInstr &MI, MachineOperand &Base, const SystemZInstrInfo *TII) { if (Base.isReg()) return Base.getReg(); - MachineBasicBlock *MBB = MI->getParent(); + MachineBasicBlock *MBB = MI.getParent(); MachineFunction &MF = *MBB->getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); - BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg) - .addOperand(Base).addImm(0).addReg(0); + BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg) + .addOperand(Base) + .addImm(0) + .addReg(0); return Reg; } // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI. MachineBasicBlock * -SystemZTargetLowering::emitSelect(MachineInstr *MI, +SystemZTargetLowering::emitSelect(MachineInstr &MI, MachineBasicBlock *MBB) const { const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); - unsigned DestReg = MI->getOperand(0).getReg(); - unsigned TrueReg = MI->getOperand(1).getReg(); - unsigned FalseReg = MI->getOperand(2).getReg(); - unsigned CCValid = MI->getOperand(3).getImm(); - unsigned CCMask = MI->getOperand(4).getImm(); - DebugLoc DL = MI->getDebugLoc(); + unsigned DestReg = MI.getOperand(0).getReg(); + unsigned TrueReg = MI.getOperand(1).getReg(); + unsigned FalseReg = MI.getOperand(2).getReg(); + unsigned CCValid = MI.getOperand(3).getImm(); + unsigned CCMask = MI.getOperand(4).getImm(); + DebugLoc DL = MI.getDebugLoc(); MachineBasicBlock *StartMBB = MBB; MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB); @@ -5138,7 +5140,7 @@ .addReg(TrueReg).addMBB(StartMBB) .addReg(FalseReg).addMBB(FalseMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return JoinMBB; } @@ -5146,21 +5148,21 @@ // StoreOpcode is the store to use and Invert says whether the store should // happen when the condition is false rather than true. If a STORE ON // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0. -MachineBasicBlock * -SystemZTargetLowering::emitCondStore(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned StoreOpcode, unsigned STOCOpcode, - bool Invert) const { +MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI, + MachineBasicBlock *MBB, + unsigned StoreOpcode, + unsigned STOCOpcode, + bool Invert) const { const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); - unsigned SrcReg = MI->getOperand(0).getReg(); - MachineOperand Base = MI->getOperand(1); - int64_t Disp = MI->getOperand(2).getImm(); - unsigned IndexReg = MI->getOperand(3).getReg(); - unsigned CCValid = MI->getOperand(4).getImm(); - unsigned CCMask = MI->getOperand(5).getImm(); - DebugLoc DL = MI->getDebugLoc(); + unsigned SrcReg = MI.getOperand(0).getReg(); + MachineOperand Base = MI.getOperand(1); + int64_t Disp = MI.getOperand(2).getImm(); + unsigned IndexReg = MI.getOperand(3).getReg(); + unsigned CCValid = MI.getOperand(4).getImm(); + unsigned CCMask = MI.getOperand(5).getImm(); + DebugLoc DL = MI.getDebugLoc(); StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp); @@ -5173,7 +5175,7 @@ BuildMI(*MBB, MI, DL, TII->get(STOCOpcode)) .addReg(SrcReg).addOperand(Base).addImm(Disp) .addImm(CCValid).addImm(CCMask); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } @@ -5202,7 +5204,7 @@ .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg); MBB->addSuccessor(JoinMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return JoinMBB; } @@ -5213,12 +5215,9 @@ // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize // is one of the operands. Invert says whether the field should be // inverted after performing BinOpcode (e.g. for NAND). -MachineBasicBlock * -SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned BinOpcode, - unsigned BitSize, - bool Invert) const { +MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode, + unsigned BitSize, bool Invert) const { MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); @@ -5227,15 +5226,15 @@ // Extract the operands. Base can be a register or a frame index. // Src2 can be a register or immediate. - unsigned Dest = MI->getOperand(0).getReg(); - MachineOperand Base = earlyUseOperand(MI->getOperand(1)); - int64_t Disp = MI->getOperand(2).getImm(); - MachineOperand Src2 = earlyUseOperand(MI->getOperand(3)); - unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0); - unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0); - DebugLoc DL = MI->getDebugLoc(); + unsigned Dest = MI.getOperand(0).getReg(); + MachineOperand Base = earlyUseOperand(MI.getOperand(1)); + int64_t Disp = MI.getOperand(2).getImm(); + MachineOperand Src2 = earlyUseOperand(MI.getOperand(3)); + unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0); + unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0); + DebugLoc DL = MI.getDebugLoc(); if (IsSubWord) - BitSize = MI->getOperand(6).getImm(); + BitSize = MI.getOperand(6).getImm(); // Subword operations use 32-bit registers. const TargetRegisterClass *RC = (BitSize <= 32 ? @@ -5323,7 +5322,7 @@ MBB->addSuccessor(LoopMBB); MBB->addSuccessor(DoneMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return DoneMBB; } @@ -5333,12 +5332,9 @@ // minimum or maximum value. KeepOldMask is the BRC condition-code mask // for when the current field should be kept. BitSize is the width of // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction. -MachineBasicBlock * -SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned CompareOpcode, - unsigned KeepOldMask, - unsigned BitSize) const { +MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode, + unsigned KeepOldMask, unsigned BitSize) const { MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); @@ -5346,15 +5342,15 @@ bool IsSubWord = (BitSize < 32); // Extract the operands. Base can be a register or a frame index. - unsigned Dest = MI->getOperand(0).getReg(); - MachineOperand Base = earlyUseOperand(MI->getOperand(1)); - int64_t Disp = MI->getOperand(2).getImm(); - unsigned Src2 = MI->getOperand(3).getReg(); - unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0); - unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0); - DebugLoc DL = MI->getDebugLoc(); + unsigned Dest = MI.getOperand(0).getReg(); + MachineOperand Base = earlyUseOperand(MI.getOperand(1)); + int64_t Disp = MI.getOperand(2).getImm(); + unsigned Src2 = MI.getOperand(3).getReg(); + unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0); + unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0); + DebugLoc DL = MI.getDebugLoc(); if (IsSubWord) - BitSize = MI->getOperand(6).getImm(); + BitSize = MI.getOperand(6).getImm(); // Subword operations use 32-bit registers. const TargetRegisterClass *RC = (BitSize <= 32 ? @@ -5442,14 +5438,14 @@ MBB->addSuccessor(LoopMBB); MBB->addSuccessor(DoneMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return DoneMBB; } // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW // instruction MI. MachineBasicBlock * -SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI, +SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI, MachineBasicBlock *MBB) const { MachineFunction &MF = *MBB->getParent(); @@ -5458,15 +5454,15 @@ MachineRegisterInfo &MRI = MF.getRegInfo(); // Extract the operands. Base can be a register or a frame index. - unsigned Dest = MI->getOperand(0).getReg(); - MachineOperand Base = earlyUseOperand(MI->getOperand(1)); - int64_t Disp = MI->getOperand(2).getImm(); - unsigned OrigCmpVal = MI->getOperand(3).getReg(); - unsigned OrigSwapVal = MI->getOperand(4).getReg(); - unsigned BitShift = MI->getOperand(5).getReg(); - unsigned NegBitShift = MI->getOperand(6).getReg(); - int64_t BitSize = MI->getOperand(7).getImm(); - DebugLoc DL = MI->getDebugLoc(); + unsigned Dest = MI.getOperand(0).getReg(); + MachineOperand Base = earlyUseOperand(MI.getOperand(1)); + int64_t Disp = MI.getOperand(2).getImm(); + unsigned OrigCmpVal = MI.getOperand(3).getReg(); + unsigned OrigSwapVal = MI.getOperand(4).getReg(); + unsigned BitShift = MI.getOperand(5).getReg(); + unsigned NegBitShift = MI.getOperand(6).getReg(); + int64_t BitSize = MI.getOperand(7).getImm(); + DebugLoc DL = MI.getDebugLoc(); const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass; @@ -5557,7 +5553,7 @@ MBB->addSuccessor(LoopMBB); MBB->addSuccessor(DoneMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return DoneMBB; } @@ -5565,18 +5561,18 @@ // if the high register of the GR128 value must be cleared or false if // it's "don't care". SubReg is subreg_l32 when extending a GR32 // and subreg_l64 when extending a GR64. -MachineBasicBlock * -SystemZTargetLowering::emitExt128(MachineInstr *MI, - MachineBasicBlock *MBB, - bool ClearEven, unsigned SubReg) const { +MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI, + MachineBasicBlock *MBB, + bool ClearEven, + unsigned SubReg) const { MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Src = MI->getOperand(1).getReg(); + unsigned Dest = MI.getOperand(0).getReg(); + unsigned Src = MI.getOperand(1).getReg(); unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128); @@ -5593,25 +5589,23 @@ BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest) .addReg(In128).addReg(Src).addImm(SubReg); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } -MachineBasicBlock * -SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned Opcode) const { +MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const { MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - MachineOperand DestBase = earlyUseOperand(MI->getOperand(0)); - uint64_t DestDisp = MI->getOperand(1).getImm(); - MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2)); - uint64_t SrcDisp = MI->getOperand(3).getImm(); - uint64_t Length = MI->getOperand(4).getImm(); + MachineOperand DestBase = earlyUseOperand(MI.getOperand(0)); + uint64_t DestDisp = MI.getOperand(1).getImm(); + MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2)); + uint64_t SrcDisp = MI.getOperand(3).getImm(); + uint64_t Length = MI.getOperand(4).getImm(); // When generating more than one CLC, all but the last will need to // branch to the end when a difference is found. @@ -5619,10 +5613,10 @@ splitBlockAfter(MI, MBB) : nullptr); // Check for the loop form, in which operand 5 is the trip count. - if (MI->getNumExplicitOperands() > 5) { + if (MI.getNumExplicitOperands() > 5) { bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase); - uint64_t StartCountReg = MI->getOperand(5).getReg(); + uint64_t StartCountReg = MI.getOperand(5).getReg(); uint64_t StartSrcReg = forceReg(MI, SrcBase, TII); uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg : forceReg(MI, DestBase, TII)); @@ -5725,15 +5719,19 @@ // Apply them using LAY if so. if (!isUInt<12>(DestDisp)) { unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); - BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg) - .addOperand(DestBase).addImm(DestDisp).addReg(0); + BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg) + .addOperand(DestBase) + .addImm(DestDisp) + .addReg(0); DestBase = MachineOperand::CreateReg(Reg, false); DestDisp = 0; } if (!isUInt<12>(SrcDisp)) { unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); - BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg) - .addOperand(SrcBase).addImm(SrcDisp).addReg(0); + BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg) + .addOperand(SrcBase) + .addImm(SrcDisp) + .addReg(0); SrcBase = MachineOperand::CreateReg(Reg, false); SrcDisp = 0; } @@ -5761,26 +5759,24 @@ MBB->addLiveIn(SystemZ::CC); } - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } // Decompose string pseudo-instruction MI into a loop that continually performs // Opcode until CC != 3. -MachineBasicBlock * -SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned Opcode) const { +MachineBasicBlock *SystemZTargetLowering::emitStringWrapper( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const { MachineFunction &MF = *MBB->getParent(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - uint64_t End1Reg = MI->getOperand(0).getReg(); - uint64_t Start1Reg = MI->getOperand(1).getReg(); - uint64_t Start2Reg = MI->getOperand(2).getReg(); - uint64_t CharReg = MI->getOperand(3).getReg(); + uint64_t End1Reg = MI.getOperand(0).getReg(); + uint64_t Start1Reg = MI.getOperand(1).getReg(); + uint64_t Start2Reg = MI.getOperand(2).getReg(); + uint64_t CharReg = MI.getOperand(3).getReg(); const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass; uint64_t This1Reg = MRI.createVirtualRegister(RC); @@ -5823,26 +5819,24 @@ DoneMBB->addLiveIn(SystemZ::CC); - MI->eraseFromParent(); + MI.eraseFromParent(); return DoneMBB; } // Update TBEGIN instruction with final opcode and register clobbers. -MachineBasicBlock * -SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned Opcode, - bool NoFloat) const { +MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode, + bool NoFloat) const { MachineFunction &MF = *MBB->getParent(); const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); // Update opcode. - MI->setDesc(TII->get(Opcode)); + MI.setDesc(TII->get(Opcode)); // We cannot handle a TBEGIN that clobbers the stack or frame pointer. // Make sure to add the corresponding GRSM bits if they are missing. - uint64_t Control = MI->getOperand(2).getImm(); + uint64_t Control = MI.getOperand(2).getImm(); static const unsigned GPRControlBit[16] = { 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000, 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100 @@ -5850,13 +5844,13 @@ Control |= GPRControlBit[15]; if (TFI->hasFP(MF)) Control |= GPRControlBit[11]; - MI->getOperand(2).setImm(Control); + MI.getOperand(2).setImm(Control); // Add GPR clobbers. for (int I = 0; I < 16; I++) { if ((Control & GPRControlBit[I]) == 0) { unsigned Reg = SystemZMC::GR64Regs[I]; - MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + MI.addOperand(MachineOperand::CreateReg(Reg, true, true)); } } @@ -5865,12 +5859,12 @@ if (Subtarget.hasVector()) { for (int I = 0; I < 32; I++) { unsigned Reg = SystemZMC::VR128Regs[I]; - MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + MI.addOperand(MachineOperand::CreateReg(Reg, true, true)); } } else { for (int I = 0; I < 16; I++) { unsigned Reg = SystemZMC::FP64Regs[I]; - MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + MI.addOperand(MachineOperand::CreateReg(Reg, true, true)); } } } @@ -5878,17 +5872,15 @@ return MBB; } -MachineBasicBlock * -SystemZTargetLowering::emitLoadAndTestCmp0(MachineInstr *MI, - MachineBasicBlock *MBB, - unsigned Opcode) const { +MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0( + MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const { MachineFunction &MF = *MBB->getParent(); MachineRegisterInfo *MRI = &MF.getRegInfo(); const SystemZInstrInfo *TII = static_cast(Subtarget.getInstrInfo()); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - unsigned SrcReg = MI->getOperand(0).getReg(); + unsigned SrcReg = MI.getOperand(0).getReg(); // Create new virtual register of the same class as source. const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); @@ -5898,14 +5890,14 @@ // well. BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg) .addReg(SrcReg); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } -MachineBasicBlock *SystemZTargetLowering:: -EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const { - switch (MI->getOpcode()) { +MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB) const { + switch (MI.getOpcode()) { case SystemZ::Select32Mux: case SystemZ::Select32: case SystemZ::SelectF32: Index: lib/Target/X86/X86ISelLowering.h =================================================================== --- lib/Target/X86/X86ISelLowering.h +++ lib/Target/X86/X86ISelLowering.h @@ -750,9 +750,8 @@ bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *MBB) const override; - + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; /// This method returns the name of a target specific DAG node. const char *getTargetNodeName(unsigned Opcode) const override; @@ -1161,50 +1160,50 @@ bool needsCmpXchgNb(Type *MemType) const; - void SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, + void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI) const; // Utility function to emit the low-level va_arg code for X86-64. - MachineBasicBlock *EmitVAARG64WithCustomInserter( - MachineInstr *MI, - MachineBasicBlock *MBB) const; + MachineBasicBlock * + EmitVAARG64WithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const; /// Utility function to emit the xmm reg save portion of va_start. - MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( - MachineInstr *BInstr, - MachineBasicBlock *BB) const; + MachineBasicBlock * + EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr, + MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, + MachineBasicBlock *EmitLoweredSelect(MachineInstr &I, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I, + MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredCatchRet(MachineInstr *MI, + MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredCatchPad(MachineInstr *MI, + MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, + MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, + MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI, MachineBasicBlock *BB) const; - MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, + MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *emitFMA3Instr(MachineInstr *MI, + MachineBasicBlock *emitFMA3Instr(MachineInstr &MI, MachineBasicBlock *MBB) const; - MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, + MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; /// Emit nodes that will be selected as "test Op0,Op0", or something Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -22409,9 +22409,9 @@ //===----------------------------------------------------------------------===// /// Utility function to emit xbegin specifying the start of an RTM region. -static MachineBasicBlock *emitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, +static MachineBasicBlock *emitXBegin(MachineInstr &MI, MachineBasicBlock *MBB, const TargetInstrInfo *TII) { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const BasicBlock *BB = MBB->getBasicBlock(); MachineFunction::iterator I = ++MBB->getIterator(); @@ -22455,21 +22455,21 @@ // sinkMBB: // EAX is live into the sinkMBB sinkMBB->addLiveIn(X86::EAX); - BuildMI(*sinkMBB, sinkMBB->begin(), DL, - TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) - .addReg(X86::EAX); + BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(TargetOpcode::COPY), + MI.getOperand(0).getReg()) + .addReg(X86::EAX); - MI->eraseFromParent(); + MI.eraseFromParent(); return sinkMBB; } // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 // or XMM0_V32I8 in AVX all of this code can be replaced with that // in the .td file. -static MachineBasicBlock *emitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, +static MachineBasicBlock *emitPCMPSTRM(MachineInstr &MI, MachineBasicBlock *BB, const TargetInstrInfo *TII) { unsigned Opc; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("illegal opcode!"); case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break; case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break; @@ -22481,32 +22481,31 @@ case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break; } - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); - unsigned NumArgs = MI->getNumOperands(); + unsigned NumArgs = MI.getNumOperands(); for (unsigned i = 1; i < NumArgs; ++i) { - MachineOperand &Op = MI->getOperand(i); + MachineOperand &Op = MI.getOperand(i); if (!(Op.isReg() && Op.isImplicit())) MIB.addOperand(Op); } - if (MI->hasOneMemOperand()) - MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); + if (MI.hasOneMemOperand()) + MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - BuildMI(*BB, MI, dl, - TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) - .addReg(X86::XMM0); + BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg()) + .addReg(X86::XMM0); - MI->eraseFromParent(); + MI.eraseFromParent(); return BB; } // FIXME: Custom handling because TableGen doesn't support multiple implicit // defs in an instruction pattern -static MachineBasicBlock *emitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, +static MachineBasicBlock *emitPCMPSTRI(MachineInstr &MI, MachineBasicBlock *BB, const TargetInstrInfo *TII) { unsigned Opc; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("illegal opcode!"); case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break; case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break; @@ -22518,34 +22517,33 @@ case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break; } - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); - unsigned NumArgs = MI->getNumOperands(); // remove the results + unsigned NumArgs = MI.getNumOperands(); // remove the results for (unsigned i = 1; i < NumArgs; ++i) { - MachineOperand &Op = MI->getOperand(i); + MachineOperand &Op = MI.getOperand(i); if (!(Op.isReg() && Op.isImplicit())) MIB.addOperand(Op); } - if (MI->hasOneMemOperand()) - MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); + if (MI.hasOneMemOperand()) + MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - BuildMI(*BB, MI, dl, - TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) - .addReg(X86::ECX); + BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg()) + .addReg(X86::ECX); - MI->eraseFromParent(); + MI.eraseFromParent(); return BB; } -static MachineBasicBlock *emitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB, +static MachineBasicBlock *emitWRPKRU(MachineInstr &MI, MachineBasicBlock *BB, const X86Subtarget &Subtarget) { - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); // insert input VAL into EAX BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) - .addReg(MI->getOperand(0).getReg()); + .addReg(MI.getOperand(0).getReg()); // insert zero to ECX BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::ECX); @@ -22555,13 +22553,13 @@ // insert WRPKRU instruction BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr)); - MI->eraseFromParent(); // The pseudo is gone now. + MI.eraseFromParent(); // The pseudo is gone now. return BB; } -static MachineBasicBlock *emitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB, +static MachineBasicBlock *emitRDPKRU(MachineInstr &MI, MachineBasicBlock *BB, const X86Subtarget &Subtarget) { - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); // insert zero to ECX @@ -22569,40 +22567,40 @@ // insert RDPKRU instruction BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr)); - BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) - .addReg(X86::EAX); + BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg()) + .addReg(X86::EAX); - MI->eraseFromParent(); // The pseudo is gone now. + MI.eraseFromParent(); // The pseudo is gone now. return BB; } -static MachineBasicBlock *emitMonitor(MachineInstr *MI, MachineBasicBlock *BB, +static MachineBasicBlock *emitMonitor(MachineInstr &MI, MachineBasicBlock *BB, const X86Subtarget &Subtarget, unsigned Opc) { - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); // Address into RAX/EAX, other two args into ECX, EDX. unsigned MemOpc = Subtarget.is64Bit() ? X86::LEA64r : X86::LEA32r; unsigned MemReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); for (int i = 0; i < X86::AddrNumOperands; ++i) - MIB.addOperand(MI->getOperand(i)); + MIB.addOperand(MI.getOperand(i)); unsigned ValOps = X86::AddrNumOperands; BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) - .addReg(MI->getOperand(ValOps).getReg()); + .addReg(MI.getOperand(ValOps).getReg()); BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) - .addReg(MI->getOperand(ValOps+1).getReg()); + .addReg(MI.getOperand(ValOps + 1).getReg()); // The instruction doesn't actually take any operands though. BuildMI(*BB, MI, dl, TII->get(Opc)); - MI->eraseFromParent(); // The pseudo is gone now. + MI.eraseFromParent(); // The pseudo is gone now. return BB; } MachineBasicBlock * -X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI, +X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const { // Emit va_arg instruction on X86-64. @@ -22614,31 +22612,31 @@ // 8 ) Align : Alignment of type // 9 ) EFLAGS (implicit-def) - assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); + assert(MI.getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); static_assert(X86::AddrNumOperands == 5, "VAARG_64 assumes 5 address operands"); - unsigned DestReg = MI->getOperand(0).getReg(); - MachineOperand &Base = MI->getOperand(1); - MachineOperand &Scale = MI->getOperand(2); - MachineOperand &Index = MI->getOperand(3); - MachineOperand &Disp = MI->getOperand(4); - MachineOperand &Segment = MI->getOperand(5); - unsigned ArgSize = MI->getOperand(6).getImm(); - unsigned ArgMode = MI->getOperand(7).getImm(); - unsigned Align = MI->getOperand(8).getImm(); + unsigned DestReg = MI.getOperand(0).getReg(); + MachineOperand &Base = MI.getOperand(1); + MachineOperand &Scale = MI.getOperand(2); + MachineOperand &Index = MI.getOperand(3); + MachineOperand &Disp = MI.getOperand(4); + MachineOperand &Segment = MI.getOperand(5); + unsigned ArgSize = MI.getOperand(6).getImm(); + unsigned ArgMode = MI.getOperand(7).getImm(); + unsigned Align = MI.getOperand(8).getImm(); // Memory Reference - assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); - MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); - MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + assert(MI.hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); + MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin(); + MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end(); // Machine Information const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // struct va_list { // i32 gp_offset @@ -22849,15 +22847,13 @@ } // Erase the pseudo instruction - MI->eraseFromParent(); + MI.eraseFromParent(); return endMBB; } -MachineBasicBlock * -X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( - MachineInstr *MI, - MachineBasicBlock *MBB) const { +MachineBasicBlock *X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *MBB) const { // Emit code to save XMM registers to the stack. The ABI says that the // number of registers to save is given in %al, so it's theoretically // possible to do an indirect jump trick to avoid saving all of them, @@ -22889,11 +22885,11 @@ // Now add the instructions. const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); - unsigned CountReg = MI->getOperand(0).getReg(); - int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); - int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); + unsigned CountReg = MI.getOperand(0).getReg(); + int64_t RegSaveFrameIndex = MI.getOperand(1).getImm(); + int64_t VarArgsFPOffset = MI.getOperand(2).getImm(); if (!Subtarget.isCallingConvWin64(F->getFunction()->getCallingConv())) { // If %al is 0, branch around the XMM save block. @@ -22904,29 +22900,29 @@ // Make sure the last operand is EFLAGS, which gets clobbered by the branch // that was just emitted, but clearly shouldn't be "saved". - assert((MI->getNumOperands() <= 3 || - !MI->getOperand(MI->getNumOperands() - 1).isReg() || - MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS) - && "Expected last argument to be EFLAGS"); + assert((MI.getNumOperands() <= 3 || + !MI.getOperand(MI.getNumOperands() - 1).isReg() || + MI.getOperand(MI.getNumOperands() - 1).getReg() == X86::EFLAGS) && + "Expected last argument to be EFLAGS"); unsigned MOVOpc = Subtarget.hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr; // In the XMM save block, save all the XMM argument registers. - for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) { + for (int i = 3, e = MI.getNumOperands() - 1; i != e; ++i) { int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; MachineMemOperand *MMO = F->getMachineMemOperand( MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset), MachineMemOperand::MOStore, /*Size=*/16, /*Align=*/16); BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) - .addFrameIndex(RegSaveFrameIndex) - .addImm(/*Scale=*/1) - .addReg(/*IndexReg=*/0) - .addImm(/*Disp=*/Offset) - .addReg(/*Segment=*/0) - .addReg(MI->getOperand(i).getReg()) - .addMemOperand(MMO); + .addFrameIndex(RegSaveFrameIndex) + .addImm(/*Scale=*/1) + .addReg(/*IndexReg=*/0) + .addImm(/*Disp=*/Offset) + .addReg(/*Segment=*/0) + .addReg(MI.getOperand(i).getReg()) + .addMemOperand(MMO); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return EndMBB; } @@ -22970,8 +22966,8 @@ // Return true if it is OK for this CMOV pseudo-opcode to be cascaded // together with other CMOV pseudo-opcodes into a single basic-block with // conditional jump around it. -static bool isCMOVPseudo(MachineInstr *MI) { - switch (MI->getOpcode()) { +static bool isCMOVPseudo(MachineInstr &MI) { + switch (MI.getOpcode()) { case X86::CMOV_FR32: case X86::CMOV_FR64: case X86::CMOV_GR8: @@ -23001,10 +22997,10 @@ } MachineBasicBlock * -X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, +X86TargetLowering::EmitLoweredSelect(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -23123,8 +23119,8 @@ // retq // MachineInstr *CascadedCMOV = nullptr; - MachineInstr *LastCMOV = MI; - X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm()); + MachineInstr *LastCMOV = &MI; + X86::CondCode CC = X86::CondCode(MI.getOperand(3).getImm()); X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC); MachineBasicBlock::iterator NextMIIt = std::next(MachineBasicBlock::iterator(MI)); @@ -23135,8 +23131,7 @@ if (isCMOVPseudo(MI)) { // See if we have a string of CMOVS with the same condition. - while (NextMIIt != BB->end() && - isCMOVPseudo(NextMIIt) && + while (NextMIIt != BB->end() && isCMOVPseudo(*NextMIIt) && (NextMIIt->getOperand(3).getImm() == CC || NextMIIt->getOperand(3).getImm() == OppCC)) { LastCMOV = &*NextMIIt; @@ -23146,10 +23141,10 @@ // This checks for case 2, but only do this if we didn't already find // case 1, as indicated by LastCMOV == MI. - if (LastCMOV == MI && - NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() && - NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() && - NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg() && + if (LastCMOV == &MI && NextMIIt != BB->end() && + NextMIIt->getOpcode() == MI.getOpcode() && + NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() && + NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() && NextMIIt->getOperand(1).isKill()) { CascadedCMOV = &*NextMIIt; } @@ -23262,12 +23257,12 @@ // If we have a cascaded CMOV, the second Jcc provides the same incoming // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes). if (CascadedCMOV) { - MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB); + MIB.addReg(MI.getOperand(2).getReg()).addMBB(jcc1MBB); // Copy the PHI result to the register defined by the second CMOV. BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())), DL, TII->get(TargetOpcode::COPY), CascadedCMOV->getOperand(0).getReg()) - .addReg(MI->getOperand(0).getReg()); + .addReg(MI.getOperand(0).getReg()); CascadedCMOV->eraseFromParent(); } @@ -23279,7 +23274,7 @@ } MachineBasicBlock * -X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI, +X86TargetLowering::EmitLoweredAtomicFP(MachineInstr &MI, MachineBasicBlock *BB) const { // Combine the following atomic floating-point modification pattern: // a.store(reg OP a.load(acquire), release) @@ -23288,7 +23283,7 @@ // movss %xmm, (%gpr) // Or sd equivalent for 64-bit operations. unsigned MOp, FOp; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP"); case X86::RELEASE_FADD32mr: FOp = X86::ADDSSrm; @@ -23300,16 +23295,16 @@ break; } const X86InstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); unsigned ValOpIdx = X86::AddrNumOperands; - unsigned VSrc = MI->getOperand(ValOpIdx).getReg(); + unsigned VSrc = MI.getOperand(ValOpIdx).getReg(); MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(FOp), MRI.createVirtualRegister(MRI.getRegClass(VSrc))) .addReg(VSrc); for (int i = 0; i < X86::AddrNumOperands; ++i) { - MachineOperand &Operand = MI->getOperand(i); + MachineOperand &Operand = MI.getOperand(i); // Clear any kill flags on register operands as we'll create a second // instruction using the same address operands. if (Operand.isReg()) @@ -23319,18 +23314,18 @@ MachineInstr *FOpMI = MIB; MIB = BuildMI(*BB, MI, DL, TII->get(MOp)); for (int i = 0; i < X86::AddrNumOperands; ++i) - MIB.addOperand(MI->getOperand(i)); + MIB.addOperand(MI.getOperand(i)); MIB.addReg(FOpMI->getOperand(0).getReg(), RegState::Kill); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * -X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, +X86TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI, MachineBasicBlock *BB) const { MachineFunction *MF = BB->getParent(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); assert(MF->shouldSplitStack()); @@ -23366,11 +23361,12 @@ getRegClassFor(getPointerTy(MF->getDataLayout())); unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), - bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), - tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), - SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), - sizeVReg = MI->getOperand(1).getReg(), - physSPReg = IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP; + bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), + tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), + SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), + sizeVReg = MI.getOperand(1).getReg(), + physSPReg = + IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP; MachineFunction::iterator MBBIter = ++BB->getIterator(); @@ -23445,24 +23441,26 @@ // Take care of the PHI nodes. BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), - MI->getOperand(0).getReg()) - .addReg(mallocPtrVReg).addMBB(mallocMBB) - .addReg(bumpSPPtrVReg).addMBB(bumpMBB); + MI.getOperand(0).getReg()) + .addReg(mallocPtrVReg) + .addMBB(mallocMBB) + .addReg(bumpSPPtrVReg) + .addMBB(bumpMBB); // Delete the original pseudo instruction. - MI->eraseFromParent(); + MI.eraseFromParent(); // And we're done. return continueMBB; } MachineBasicBlock * -X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI, +X86TargetLowering::EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) const { MachineFunction *MF = BB->getParent(); const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB(); - DebugLoc DL = MI->getDebugLoc(); + MachineBasicBlock *TargetMBB = MI.getOperand(0).getMBB(); + DebugLoc DL = MI.getDebugLoc(); assert(!isAsynchronousEHPersonality( classifyEHPersonality(MF->getFunction()->getPersonalityFn())) && @@ -23480,7 +23478,7 @@ MF->insert(std::next(BB->getIterator()), RestoreMBB); RestoreMBB->transferSuccessorsAndUpdatePHIs(BB); BB->addSuccessor(RestoreMBB); - MI->getOperand(0).setMBB(RestoreMBB); + MI.getOperand(0).setMBB(RestoreMBB); auto RestoreMBBI = RestoreMBB->begin(); BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE)); @@ -23489,7 +23487,7 @@ } MachineBasicBlock * -X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI, +X86TargetLowering::EmitLoweredCatchPad(MachineInstr &MI, MachineBasicBlock *BB) const { MachineFunction *MF = BB->getParent(); const Constant *PerFn = MF->getFunction()->getPersonalityFn(); @@ -23497,15 +23495,15 @@ // Only 32-bit SEH requires special handling for catchpad. if (IsSEH && Subtarget.is32Bit()) { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE)); } - MI->eraseFromParent(); + MI.eraseFromParent(); return BB; } MachineBasicBlock * -X86TargetLowering::EmitLoweredTLSAddr(MachineInstr *MI, +X86TargetLowering::EmitLoweredTLSAddr(MachineInstr &MI, MachineBasicBlock *BB) const { // So, here we replace TLSADDR with the sequence: // adjust_stackdown -> TLSADDR -> adjust_stackup. @@ -23513,7 +23511,7 @@ // inside MC, therefore without the two markers shrink-wrapping // may push the prologue/epilogue pass them. const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction &MF = *BB->getParent(); // Emit CALLSEQ_START right before the instruction. @@ -23534,7 +23532,7 @@ } MachineBasicBlock * -X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, +X86TargetLowering::EmitLoweredTLSCall(MachineInstr &MI, MachineBasicBlock *BB) const { // This is pretty easy. We're taking the value that we received from // our load from the relocation, sticking it in either RDI (x86-64) @@ -23542,10 +23540,10 @@ // be in the normal return register. MachineFunction *F = BB->getParent(); const X86InstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); assert(Subtarget.isTargetDarwin() && "Darwin only instr emitted?"); - assert(MI->getOperand(3).isGlobal() && "This should be a global"); + assert(MI.getOperand(3).isGlobal() && "This should be a global"); // Get a register mask for the lowered call. // FIXME: The 32-bit calls have non-standard calling conventions. Use a @@ -23555,48 +23553,51 @@ Subtarget.getRegisterInfo()->getDarwinTLSCallPreservedMask() : Subtarget.getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C); if (Subtarget.is64Bit()) { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV64rm), X86::RDI) - .addReg(X86::RIP) - .addImm(0).addReg(0) - .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, - MI->getOperand(3).getTargetFlags()) - .addReg(0); + MachineInstrBuilder MIB = + BuildMI(*BB, MI, DL, TII->get(X86::MOV64rm), X86::RDI) + .addReg(X86::RIP) + .addImm(0) + .addReg(0) + .addGlobalAddress(MI.getOperand(3).getGlobal(), 0, + MI.getOperand(3).getTargetFlags()) + .addReg(0); MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); addDirectMem(MIB, X86::RDI); MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); } else if (!isPositionIndependent()) { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV32rm), X86::EAX) - .addReg(0) - .addImm(0).addReg(0) - .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, - MI->getOperand(3).getTargetFlags()) - .addReg(0); + MachineInstrBuilder MIB = + BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX) + .addReg(0) + .addImm(0) + .addReg(0) + .addGlobalAddress(MI.getOperand(3).getGlobal(), 0, + MI.getOperand(3).getTargetFlags()) + .addReg(0); MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); addDirectMem(MIB, X86::EAX); MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); } else { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV32rm), X86::EAX) - .addReg(TII->getGlobalBaseReg(F)) - .addImm(0).addReg(0) - .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, - MI->getOperand(3).getTargetFlags()) - .addReg(0); + MachineInstrBuilder MIB = + BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX) + .addReg(TII->getGlobalBaseReg(F)) + .addImm(0) + .addReg(0) + .addGlobalAddress(MI.getOperand(3).getGlobal(), 0, + MI.getOperand(3).getTargetFlags()) + .addReg(0); MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); addDirectMem(MIB, X86::EAX); MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } MachineBasicBlock * -X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, +X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -23605,15 +23606,15 @@ MachineFunction::iterator I = ++MBB->getIterator(); // Memory Reference - MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); - MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin(); + MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end(); unsigned DstReg; unsigned MemOpndSlot = 0; unsigned CurOp = 0; - DstReg = MI->getOperand(CurOp++).getReg(); + DstReg = MI.getOperand(CurOp++).getReg(); const TargetRegisterClass *RC = MRI.getRegClass(DstReg); assert(RC->hasType(MVT::i32) && "Invalid destination!"); unsigned mainDstReg = MRI.createVirtualRegister(RC); @@ -23691,9 +23692,9 @@ MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc)); for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { if (i == X86::AddrDisp) - MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset); + MIB.addDisp(MI.getOperand(MemOpndSlot + i), LabelOffset); else - MIB.addOperand(MI->getOperand(MemOpndSlot + i)); + MIB.addOperand(MI.getOperand(MemOpndSlot + i)); } if (!UseImmLabel) MIB.addReg(LabelReg); @@ -23737,21 +23738,21 @@ BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB); restoreMBB->addSuccessor(sinkMBB); - MI->eraseFromParent(); + MI.eraseFromParent(); return sinkMBB; } MachineBasicBlock * -X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, +X86TargetLowering::emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); // Memory Reference - MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); - MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin(); + MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end(); MVT PVT = getPointerTy(MF->getDataLayout()); assert((PVT == MVT::i64 || PVT == MVT::i32) && @@ -23776,38 +23777,38 @@ // Reload FP MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP); for (unsigned i = 0; i < X86::AddrNumOperands; ++i) - MIB.addOperand(MI->getOperand(i)); + MIB.addOperand(MI.getOperand(i)); MIB.setMemRefs(MMOBegin, MMOEnd); // Reload IP MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp); for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { if (i == X86::AddrDisp) - MIB.addDisp(MI->getOperand(i), LabelOffset); + MIB.addDisp(MI.getOperand(i), LabelOffset); else - MIB.addOperand(MI->getOperand(i)); + MIB.addOperand(MI.getOperand(i)); } MIB.setMemRefs(MMOBegin, MMOEnd); // Reload SP MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP); for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { if (i == X86::AddrDisp) - MIB.addDisp(MI->getOperand(i), SPOffset); + MIB.addDisp(MI.getOperand(i), SPOffset); else - MIB.addOperand(MI->getOperand(i)); + MIB.addOperand(MI.getOperand(i)); } MIB.setMemRefs(MMOBegin, MMOEnd); // Jump BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp); - MI->eraseFromParent(); + MI.eraseFromParent(); return MBB; } -void X86TargetLowering::SetupEntryBlockForSjLj(MachineInstr *MI, +void X86TargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction *MF = MBB->getParent(); MachineRegisterInfo *MRI = &MF->getRegInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); @@ -23856,9 +23857,9 @@ } MachineBasicBlock * -X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI, +X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); MachineFunction *MF = BB->getParent(); MachineModuleInfo *MMI = &MF->getMMI(); MachineFrameInfo *MFI = MF->getFrameInfo(); @@ -24033,7 +24034,7 @@ LP->setIsEHPad(false); // The instruction is gone now. - MI->eraseFromParent(); + MI.eraseFromParent(); return BB; } @@ -24042,9 +24043,9 @@ // to remove extra copies in the loop. // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937). MachineBasicBlock * -X86TargetLowering::emitFMA3Instr(MachineInstr *MI, +X86TargetLowering::emitFMA3Instr(MachineInstr &MI, MachineBasicBlock *MBB) const { - MachineOperand &AddendOp = MI->getOperand(3); + MachineOperand &AddendOp = MI.getOperand(3); // Bail out early if the addend isn't a register - we can't switch these. if (!AddendOp.isReg()) @@ -24075,55 +24076,120 @@ assert(AddendDef.getOperand(i).isReg()); MachineOperand PHISrcOp = AddendDef.getOperand(i); MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg()); - if (&PHISrcInst == MI) { + if (&PHISrcInst == &MI) { // Found a matching instruction. unsigned NewFMAOpc = 0; - switch (MI->getOpcode()) { - case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break; - case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break; - case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break; - case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break; - case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break; - case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break; - case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break; - case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break; - case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break; - case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break; - case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break; - case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break; - case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break; - case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break; - case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break; - case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break; - case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break; - case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break; - case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break; - case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break; - - case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break; - case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break; - case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break; - case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break; - case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break; - case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break; - case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break; - case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break; - case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break; - case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break; - case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break; - case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break; - default: llvm_unreachable("Unrecognized FMA variant."); + switch (MI.getOpcode()) { + case X86::VFMADDPDr213r: + NewFMAOpc = X86::VFMADDPDr231r; + break; + case X86::VFMADDPSr213r: + NewFMAOpc = X86::VFMADDPSr231r; + break; + case X86::VFMADDSDr213r: + NewFMAOpc = X86::VFMADDSDr231r; + break; + case X86::VFMADDSSr213r: + NewFMAOpc = X86::VFMADDSSr231r; + break; + case X86::VFMSUBPDr213r: + NewFMAOpc = X86::VFMSUBPDr231r; + break; + case X86::VFMSUBPSr213r: + NewFMAOpc = X86::VFMSUBPSr231r; + break; + case X86::VFMSUBSDr213r: + NewFMAOpc = X86::VFMSUBSDr231r; + break; + case X86::VFMSUBSSr213r: + NewFMAOpc = X86::VFMSUBSSr231r; + break; + case X86::VFNMADDPDr213r: + NewFMAOpc = X86::VFNMADDPDr231r; + break; + case X86::VFNMADDPSr213r: + NewFMAOpc = X86::VFNMADDPSr231r; + break; + case X86::VFNMADDSDr213r: + NewFMAOpc = X86::VFNMADDSDr231r; + break; + case X86::VFNMADDSSr213r: + NewFMAOpc = X86::VFNMADDSSr231r; + break; + case X86::VFNMSUBPDr213r: + NewFMAOpc = X86::VFNMSUBPDr231r; + break; + case X86::VFNMSUBPSr213r: + NewFMAOpc = X86::VFNMSUBPSr231r; + break; + case X86::VFNMSUBSDr213r: + NewFMAOpc = X86::VFNMSUBSDr231r; + break; + case X86::VFNMSUBSSr213r: + NewFMAOpc = X86::VFNMSUBSSr231r; + break; + case X86::VFMADDSUBPDr213r: + NewFMAOpc = X86::VFMADDSUBPDr231r; + break; + case X86::VFMADDSUBPSr213r: + NewFMAOpc = X86::VFMADDSUBPSr231r; + break; + case X86::VFMSUBADDPDr213r: + NewFMAOpc = X86::VFMSUBADDPDr231r; + break; + case X86::VFMSUBADDPSr213r: + NewFMAOpc = X86::VFMSUBADDPSr231r; + break; + + case X86::VFMADDPDr213rY: + NewFMAOpc = X86::VFMADDPDr231rY; + break; + case X86::VFMADDPSr213rY: + NewFMAOpc = X86::VFMADDPSr231rY; + break; + case X86::VFMSUBPDr213rY: + NewFMAOpc = X86::VFMSUBPDr231rY; + break; + case X86::VFMSUBPSr213rY: + NewFMAOpc = X86::VFMSUBPSr231rY; + break; + case X86::VFNMADDPDr213rY: + NewFMAOpc = X86::VFNMADDPDr231rY; + break; + case X86::VFNMADDPSr213rY: + NewFMAOpc = X86::VFNMADDPSr231rY; + break; + case X86::VFNMSUBPDr213rY: + NewFMAOpc = X86::VFNMSUBPDr231rY; + break; + case X86::VFNMSUBPSr213rY: + NewFMAOpc = X86::VFNMSUBPSr231rY; + break; + case X86::VFMADDSUBPDr213rY: + NewFMAOpc = X86::VFMADDSUBPDr231rY; + break; + case X86::VFMADDSUBPSr213rY: + NewFMAOpc = X86::VFMADDSUBPSr231rY; + break; + case X86::VFMSUBADDPDr213rY: + NewFMAOpc = X86::VFMSUBADDPDr231rY; + break; + case X86::VFMSUBADDPSr213rY: + NewFMAOpc = X86::VFMSUBADDPSr231rY; + break; + default: + llvm_unreachable("Unrecognized FMA variant."); } const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); MachineInstrBuilder MIB = - BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc)) - .addOperand(MI->getOperand(0)) - .addOperand(MI->getOperand(3)) - .addOperand(MI->getOperand(2)) - .addOperand(MI->getOperand(1)); + BuildMI(MF, MI.getDebugLoc(), TII.get(NewFMAOpc)) + .addOperand(MI.getOperand(0)) + .addOperand(MI.getOperand(3)) + .addOperand(MI.getOperand(2)) + .addOperand(MI.getOperand(1)); MBB->insert(MachineBasicBlock::iterator(MI), MIB); - MI->eraseFromParent(); + MI.eraseFromParent(); } } @@ -24131,9 +24197,9 @@ } MachineBasicBlock * -X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("Unexpected instr type to insert"); case X86::TAILJMPd64: case X86::TAILJMPr64: @@ -24187,36 +24253,35 @@ case X86::RDFLAGS32: case X86::RDFLAGS64: { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned PushF = - MI->getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64; - unsigned Pop = - MI->getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r; + MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64; + unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r; MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF)); // Permit reads of the FLAGS register without it being defined. // This intrinsic exists to read external processor state in flags, such as // the trap flag, interrupt flag, and direction flag, none of which are // modeled by the backend. Push->getOperand(2).setIsUndef(); - BuildMI(*BB, MI, DL, TII->get(Pop), MI->getOperand(0).getReg()); + BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg()); - MI->eraseFromParent(); // The pseudo is gone now. + MI.eraseFromParent(); // The pseudo is gone now. return BB; } case X86::WRFLAGS32: case X86::WRFLAGS64: { - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned Push = - MI->getOpcode() == X86::WRFLAGS32 ? X86::PUSH32r : X86::PUSH64r; + MI.getOpcode() == X86::WRFLAGS32 ? X86::PUSH32r : X86::PUSH64r; unsigned PopF = - MI->getOpcode() == X86::WRFLAGS32 ? X86::POPF32 : X86::POPF64; - BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI->getOperand(0).getReg()); + MI.getOpcode() == X86::WRFLAGS32 ? X86::POPF32 : X86::POPF64; + BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg()); BuildMI(*BB, MI, DL, TII->get(PopF)); - MI->eraseFromParent(); // The pseudo is gone now. + MI.eraseFromParent(); // The pseudo is gone now. return BB; } @@ -24235,7 +24300,7 @@ case X86::FP80_TO_INT64_IN_MEM: { MachineFunction *F = BB->getParent(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - DebugLoc DL = MI->getDebugLoc(); + DebugLoc DL = MI.getDebugLoc(); // Change the floating point control register to use "round towards zero" // mode when truncating to an integer value. @@ -24263,7 +24328,7 @@ // Get the X86 opcode to use. unsigned Opc; - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: llvm_unreachable("illegal opcode!"); case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; @@ -24276,15 +24341,15 @@ case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; } - X86AddressMode AM = getAddressFromInstr(MI, 0); + X86AddressMode AM = getAddressFromInstr(&MI, 0); addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) - .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); + .addReg(MI.getOperand(X86::AddrNumOperands).getReg()); // Reload the original control word now. addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } // String/text processing lowering. @@ -24389,7 +24454,7 @@ case X86::LCMPXCHG8B_SAVE_EBX: case X86::LCMPXCHG16B_SAVE_RBX: { unsigned BasePtr = - MI->getOpcode() == X86::LCMPXCHG8B_SAVE_EBX ? X86::EBX : X86::RBX; + MI.getOpcode() == X86::LCMPXCHG8B_SAVE_EBX ? X86::EBX : X86::RBX; if (!BB->isLiveIn(BasePtr)) BB->addLiveIn(BasePtr); return BB; Index: lib/Target/XCore/XCoreISelLowering.h =================================================================== --- lib/Target/XCore/XCoreISelLowering.h +++ lib/Target/XCore/XCoreISelLowering.h @@ -119,8 +119,8 @@ const char *getTargetNodeName(unsigned Opcode) const override; MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *MBB) const override; + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override; Index: lib/Target/XCore/XCoreISelLowering.cpp =================================================================== --- lib/Target/XCore/XCoreISelLowering.cpp +++ lib/Target/XCore/XCoreISelLowering.cpp @@ -1533,11 +1533,11 @@ //===----------------------------------------------------------------------===// MachineBasicBlock * -XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, +XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc dl = MI->getDebugLoc(); - assert((MI->getOpcode() == XCore::SELECT_CC) && + DebugLoc dl = MI.getDebugLoc(); + assert((MI.getOpcode() == XCore::SELECT_CC) && "Unexpected instr type to insert"); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond @@ -1570,7 +1570,8 @@ BB->addSuccessor(sinkMBB); BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) - .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); + .addReg(MI.getOperand(1).getReg()) + .addMBB(sinkMBB); // copy0MBB: // %FalseValue = ... @@ -1584,12 +1585,13 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII.get(XCore::PHI), MI->getOperand(0).getReg()) - .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) - .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); + BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(3).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; }