Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -529,11 +529,6 @@ bool AMDGPUDAGToDAGISel::isGlobalLoad(const MemSDNode *N) const { if (!N->readMem()) return false; - if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) { - if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) - return !isa(GetUnderlyingObject( - N->getMemOperand()->getValue(), CurDAG->getDataLayout())); - } return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS); } Index: llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td @@ -202,53 +202,53 @@ //===----------------------------------------------------------------------===// // 8-bit reads -def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1, - [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_8_cm : VTX_READ_8_cm <1, + [(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))] >; // 16-bit reads -def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1, - [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_16_cm : VTX_READ_16_cm <1, + [(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))] >; // 32-bit reads -def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1, - [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_32_cm : VTX_READ_32_cm <1, + [(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 64-bit reads -def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1, - [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_64_cm : VTX_READ_64_cm <1, + [(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 128-bit reads -def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1, - [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_128_cm : VTX_READ_128_cm <1, + [(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 8-bit reads -def VTX_READ_CONSTANT_8_cm : VTX_READ_8_cm <2, - [(set i32:$dst_gpr, (az_extloadi8_constant ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_8_cm : VTX_READ_8_cm <2, + [(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))] >; // 16-bit reads -def VTX_READ_CONSTANT_16_cm : VTX_READ_16_cm <2, - [(set i32:$dst_gpr, (az_extloadi16_constant ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_16_cm : VTX_READ_16_cm <2, + [(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))] >; // 32-bit reads -def VTX_READ_CONSTANT_32_cm : VTX_READ_32_cm <2, - [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_32_cm : VTX_READ_32_cm <2, + [(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; // 64-bit reads -def VTX_READ_CONSTANT_64_cm : VTX_READ_64_cm <2, - [(set v2i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_64_cm : VTX_READ_64_cm <2, + [(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; // 128-bit reads -def VTX_READ_CONSTANT_128_cm : VTX_READ_128_cm <2, - [(set v4i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_128_cm : VTX_READ_128_cm <2, + [(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; } // End isCayman Index: llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td @@ -235,53 +235,53 @@ //===----------------------------------------------------------------------===// // 8-bit reads -def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1, - [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_8_eg : VTX_READ_8_eg <1, + [(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))] >; // 16-bit reads -def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1, - [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_16_eg : VTX_READ_16_eg <1, + [(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))] >; // 32-bit reads -def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1, - [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_32_eg : VTX_READ_32_eg <1, + [(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 64-bit reads -def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1, - [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_64_eg : VTX_READ_64_eg <1, + [(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 128-bit reads -def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, - [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID1_128_eg : VTX_READ_128_eg <1, + [(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))] >; // 8-bit reads -def VTX_READ_CONSTANT_8_eg : VTX_READ_8_eg <2, - [(set i32:$dst_gpr, (az_extloadi8_constant ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_8_eg : VTX_READ_8_eg <2, + [(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))] >; // 16-bit reads -def VTX_READ_CONSTANT_16_eg : VTX_READ_16_eg <2, - [(set i32:$dst_gpr, (az_extloadi16_constant ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_16_eg : VTX_READ_16_eg <2, + [(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))] >; // 32-bit reads -def VTX_READ_CONSTANT_32_eg : VTX_READ_32_eg <2, - [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_32_eg : VTX_READ_32_eg <2, + [(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; // 64-bit reads -def VTX_READ_CONSTANT_64_eg : VTX_READ_64_eg <2, - [(set v2i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_64_eg : VTX_READ_64_eg <2, + [(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; // 128-bit reads -def VTX_READ_CONSTANT_128_eg : VTX_READ_128_eg <2, - [(set v4i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))] +def VTX_READ_ID2_128_eg : VTX_READ_128_eg <2, + [(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))] >; } // End Predicates = [isEG] Index: llvm/trunk/lib/Target/AMDGPU/R600Instructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600Instructions.td +++ llvm/trunk/lib/Target/AMDGPU/R600Instructions.td @@ -336,6 +336,31 @@ def load_param_exti8 : LoadParamFrag; def load_param_exti16 : LoadParamFrag; +class LoadVtxId1 : PatFrag < + (ops node:$ptr), (load node:$ptr), [{ + const MemSDNode *LD = cast(N); + return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || + (LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && + !isa(GetUnderlyingObject( + LD->getMemOperand()->getValue(), CurDAG->getDataLayout()))); +}]>; + +def vtx_id1_az_extloadi8 : LoadVtxId1 ; +def vtx_id1_az_extloadi16 : LoadVtxId1 ; +def vtx_id1_load : LoadVtxId1 ; + +class LoadVtxId2 : PatFrag < + (ops node:$ptr), (load node:$ptr), [{ + const MemSDNode *LD = cast(N); + return LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && + isa(GetUnderlyingObject( + LD->getMemOperand()->getValue(), CurDAG->getDataLayout())); +}]>; + +def vtx_id2_az_extloadi8 : LoadVtxId2 ; +def vtx_id2_az_extloadi16 : LoadVtxId2 ; +def vtx_id2_load : LoadVtxId2 ; + def isR600 : Predicate<"Subtarget->getGeneration() <= R600Subtarget::R700">; def isR600toCayman