Index: lib/Target/Mips/MicroMips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrInfo.td +++ lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -397,6 +397,9 @@ def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6; +let AdditionalPredicates = [InMicroMips] in +defm : MaterializeImms; + //===----------------------------------------------------------------------===// // // Instruction aliases Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -989,6 +989,12 @@ // MicroMips arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +def : MipsPat<(i32 immLi16:$imm), + (LI16_MM immLi16:$imm)>; + +let AdditionalPredicates = [InMicroMips] in +defm : MaterializeImms; + let Predicates = [InMicroMips] in { def : MipsPat<(i32 immLi16:$imm), (LI16_MM immLi16:$imm)>; Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -488,6 +488,16 @@ // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +// Materialize i64 constants. +defm : MaterializeImms; + +def : MipsPat<(i64 immZExt32Low16Zero:$imm), + (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>; + +def : MipsPat<(i64 immZExt32:$imm), + (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), + (LO16 imm:$imm))>; + // extended loads def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1033,11 +1033,23 @@ }], LO16>; // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). -def immLow16Zero : PatLeaf<(imm), [{ +def immSExt32Low16Zero : PatLeaf<(imm), [{ int64_t Val = N->getSExtValue(); return isInt<32>(Val) && !(Val & 0xffff); }]>; +// Zero-extended 32-bit unsigned int with lower 16-bit cleared. +def immZExt32Low16Zero : PatLeaf<(imm), [{ + uint64_t Val = N->getZExtValue(); + return isUInt<32>(Val) && !(Val & 0xffff); +}]>; + +// Note immediate fits as a 32 bit signed extended on target immediate. +def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>; + +// Note immediate fits as a 32 bit zero extended on target immediate. +def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; + // shamt field must fit in 5 bits. def immZExt5 : ImmLeaf; @@ -2431,19 +2443,24 @@ class StoreRegImmPat : MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; +// Materialize constants. +multiclass MaterializeImms { + // Small immediates -let AdditionalPredicates = [NotInMicroMips] in { -def : MipsPat<(i32 immSExt16:$in), - (ADDiu ZERO, imm:$in)>; -def : MipsPat<(i32 immZExt16:$in), - (ORi ZERO, imm:$in)>; -} -def : MipsPat<(i32 immLow16Zero:$in), - (LUi (HI16 imm:$in))>; +def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; +def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>; + +// Bits 32-16 set, sign/zero extended. +def : MipsPat<(VT immSExt32Low16Zero:$imm), (LUiOp (HI16 imm:$imm))>; // Arbitrary immediates -def : MipsPat<(i32 imm:$imm), - (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; +def : MipsPat<(VT immSExt32:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>; +} + +let AdditionalPredicates = [NotInMicroMips] in +defm : MaterializeImms; // Carry MipsPatterns let AdditionalPredicates = [NotInMicroMips] in { Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp =================================================================== --- lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -747,13 +747,13 @@ case ISD::Constant: { const ConstantSDNode *CN = dyn_cast(Node); + int64_t Imm = CN->getSExtValue(); unsigned Size = CN->getValueSizeInBits(0); - if (Size == 32) + if (isInt<32>(Imm)) break; MipsAnalyzeImmediate AnalyzeImm; - int64_t Imm = CN->getSExtValue(); const MipsAnalyzeImmediate::InstSeq &Seq = AnalyzeImm.Analyze(Imm, Size, false); Index: test/CodeGen/Mips/cmov.ll =================================================================== --- test/CodeGen/Mips/cmov.ll +++ test/CodeGen/Mips/cmov.ll @@ -517,18 +517,23 @@ ; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 ; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4 -; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766 -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]] -; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4 -; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5 -; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766 -; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 + +; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766 +; 64-CMOV-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4 +; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R3]] + +; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4 + +; 64-CMP-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMP-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766 +; 64-CMP-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4 ; FIXME: We can do better than this by using selccz to choose between -0 and -2 -; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]] -; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] -; 64-CMP-DAG: or $2, $[[T1]], $[[T0]] +; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R3]] +; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R3]] +; 64-CMP-DAG: or $2, $[[T0]], $[[T1]] define i64 @slti64_3(i64 %a) { entry: Index: test/CodeGen/Mips/fcmp.ll =================================================================== --- test/CodeGen/Mips/fcmp.ll +++ test/CodeGen/Mips/fcmp.ll @@ -31,7 +31,7 @@ ; 64-CMP: addiu $2, $zero, 0 -; MM-DAG: lui $2, 0 +; MM-DAG: li16 $2, 0 %1 = fcmp false float %a, %b %2 = zext i1 %1 to i32 @@ -57,7 +57,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -91,7 +91,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -125,7 +125,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -159,7 +159,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -193,7 +193,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -229,7 +229,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -266,7 +266,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -301,7 +301,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -335,7 +335,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -369,7 +369,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -403,7 +403,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -437,7 +437,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -473,7 +473,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -508,7 +508,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -550,7 +550,7 @@ ; 64-CMP: addiu $2, $zero, 0 -; MM-DAG: lui $2, 0 +; MM-DAG: li16 $2, 0 %1 = fcmp false double %a, %b %2 = zext i1 %1 to i32 @@ -576,7 +576,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -610,7 +610,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -644,7 +644,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -678,7 +678,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -712,7 +712,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -748,7 +748,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -785,7 +785,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -820,7 +820,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -854,7 +854,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -888,7 +888,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -922,7 +922,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -956,7 +956,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 @@ -992,7 +992,7 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 @@ -1027,7 +1027,7 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 Index: test/CodeGen/Mips/llvm-ir/add.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/add.ll +++ test/CodeGen/Mips/llvm-ir/add.ll @@ -284,7 +284,7 @@ ; MM32: li16 $[[T1:[0-9]+]], 4 ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] - ; MM32: lui $[[T1]], 0 + ; MM32: li16 $[[T1]], 0 ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; MM32: addu $[[T3]], $5, $[[T3]] ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] @@ -414,7 +414,7 @@ ; MM32: li16 $[[T1:[0-9]+]], 3 ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] - ; MM32: lui $[[T3:[0-9]+]], 0 + ; MM32: li16 $[[T3:[0-9]+]], 0 ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; MM32: addu $[[T4]], $5, $[[T4]] ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] Index: test/CodeGen/Mips/llvm-ir/and.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/and.ll +++ test/CodeGen/Mips/llvm-ir/and.ll @@ -155,7 +155,7 @@ ; GP64: addiu $2, $zero, 0 - ; MM: lui $2, 0 + ; MM: li16 $2, 0 %r = and i1 4, %b ret i1 %r @@ -213,7 +213,7 @@ ; GP64: andi $2, $4, 4 ; MM32: andi16 $3, $5, 4 - ; MM32: lui $2, 0 + ; MM32: li16 $2, 0 ; MM64: andi $2, $4, 4 @@ -234,9 +234,9 @@ ; GP64: daddiu $2, $zero, 0 ; MM32: andi16 $5, $7, 4 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32: li16 $2, 0 + ; MM32: li16 $3, 0 + ; MM32: li16 $4, 0 ; MM64: andi $3, $5, 4 ; MM64: daddiu $2, $zero, 0 @@ -307,7 +307,7 @@ ; GP64: andi $2, $4, 31 ; MM32: andi16 $3, $5, 31 - ; MM32: lui $2, 0 + ; MM32: li16 $2, 0 ; MM64: andi $2, $4, 31 @@ -328,9 +328,9 @@ ; GP64: daddiu $2, $zero, 0 ; MM32: andi16 $5, $7, 31 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32: li16 $2, 0 + ; MM32: li16 $3, 0 + ; MM32: li16 $4, 0 ; MM64: andi $3, $5, 31 ; MM64: daddiu $2, $zero, 0 @@ -397,7 +397,7 @@ ; GP64: andi $2, $4, 255 ; MM32: andi16 $3, $5, 255 - ; MM32: lui $2, 0 + ; MM32: li16 $2, 0 ; MM64: andi $2, $4, 255 @@ -418,9 +418,9 @@ ; GP64: daddiu $2, $zero, 0 ; MM32: andi16 $5, $7, 255 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32: li16 $2, 0 + ; MM32: li16 $3, 0 + ; MM32: li16 $4, 0 ; MM64: andi $3, $5, 255 ; MM64: daddiu $2, $zero, 0 @@ -437,7 +437,7 @@ ; GP64: addiu $2, $zero, 0 - ; MM: lui $2, 0 + ; MM: li16 $2, 0 %r = and i1 32768, %b ret i1 %r @@ -451,7 +451,7 @@ ; GP64: addiu $2, $zero, 0 - ; MM: lui $2, 0 + ; MM: li16 $2, 0 %r = and i8 32768, %b ret i8 %r @@ -498,7 +498,7 @@ ; GP64: andi $2, $4, 32768 ; MM32: andi16 $3, $5, 32768 - ; MM32: lui $2, 0 + ; MM32: li16 $2, 0 ; MM64: andi $2, $4, 32768 @@ -519,9 +519,9 @@ ; GP64: daddiu $2, $zero, 0 ; MM32: andi16 $5, $7, 32768 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32: li16 $2, 0 + ; MM32: li16 $3, 0 + ; MM32: li16 $4, 0 ; MM64: andi $3, $5, 32768 ; MM64: daddiu $2, $zero, 0 @@ -579,8 +579,8 @@ ; GP64: andi $2, $4, 65 - ; MM32: andi $3, $5, 65 - ; MM32: lui $2, 0 + ; MM32-DAG: andi $3, $5, 65 + ; MM32-DAG: li16 $2, 0 ; MM64: andi $2, $4, 65 @@ -600,10 +600,10 @@ ; GP64: andi $3, $5, 65 ; GP64: daddiu $2, $zero, 0 - ; MM32: andi $5, $7, 65 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32-DAG: andi $5, $7, 65 + ; MM32-DAG: li16 $2, 0 + ; MM32-DAG: li16 $3, 0 + ; MM32-DAG: li16 $4, 0 ; MM64: andi $3, $5, 65 ; MM64: daddiu $2, $zero, 0 @@ -620,7 +620,7 @@ ; GP64: addiu $2, $zero, 0 - ; MM: lui $2, 0 + ; MM: li16 $2, 0 %r = and i1 256, %b ret i1 %r @@ -634,7 +634,7 @@ ; GP64: addiu $2, $zero, 0 - ; MM: lui $2, 0 + ; MM: li16 $2, 0 %r = and i8 256, %b ret i8 %r @@ -669,8 +669,8 @@ ; GP64: andi $2, $4, 256 - ; MM32: andi $3, $5, 256 - ; MM32: lui $2, 0 + ; MM32-DAG: andi $3, $5, 256 + ; MM32-DAG: li16 $2, 0 ; MM64: andi $2, $4, 256 @@ -690,10 +690,10 @@ ; GP64: andi $3, $5, 256 ; GP64: daddiu $2, $zero, 0 - ; MM32: andi $5, $7, 256 - ; MM32: lui $2, 0 - ; MM32: lui $3, 0 - ; MM32: lui $4, 0 + ; MM32-DAG: andi $5, $7, 256 + ; MM32-DAG: li16 $2, 0 + ; MM32-DAG: li16 $3, 0 + ; MM32-DAG: li16 $4, 0 ; MM64: andi $3, $5, 256 ; MM64: daddiu $2, $zero, 0 Index: test/CodeGen/Mips/llvm-ir/lshr.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/lshr.ll +++ test/CodeGen/Mips/llvm-ir/lshr.ll @@ -143,7 +143,7 @@ ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: li16 $[[T8:[0-9]+]], 0 ; MMR3: movn $2, $[[T8]], $[[T6]] ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 Index: test/CodeGen/Mips/llvm-ir/ret.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/ret.ll +++ test/CodeGen/Mips/llvm-ir/ret.ll @@ -114,7 +114,7 @@ ; GPR32-DAG: ori $3, $[[T0]], 1 ; GPR32-DAG: addiu $2, $zero, 0 -; GPR64-DAG: daddiu $2, $[[T0]], 1 +; GPR64-DAG: ori $2, $[[T0]], 1 ; NOT-R6-DAG: jr $ra #