Index: include/llvm/Object/RelocVisitor.h
===================================================================
--- include/llvm/Object/RelocVisitor.h
+++ include/llvm/Object/RelocVisitor.h
@@ -139,6 +139,16 @@
           HasError = true;
           return RelocToApply();
         }
+      case Triple::amdgcn:
+        switch (RelocType) {
+        case llvm::ELF::R_AMDGPU_ABS32_LO:
+        case llvm::ELF::R_AMDGPU_ABS32_HI:
+          return visitELF_AMDGPU_32(R, Value);
+        default:
+          HasError = true;
+          return RelocToApply();
+        }
+
       default:
         HasError = true;
         return RelocToApply();
@@ -403,6 +413,12 @@
     return RelocToApply(static_cast<uint32_t>(Res), 4);
   }
 
+  // AMDGPU ELF
+  RelocToApply visitELF_AMDGPU_32(RelocationRef R, uint64_t Value) {
+    int64_t Addend = getELFAddend(R);
+    return RelocToApply(Value + Addend, 4);
+  }
+
   /// I386 COFF
   RelocToApply visitCOFF_I386_SECREL(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
Index: include/llvm/Support/ELF.h
===================================================================
--- include/llvm/Support/ELF.h
+++ include/llvm/Support/ELF.h
@@ -614,6 +614,11 @@
 #include "ELFRelocs/WebAssembly.def"
 };
 
+// ELF Relocation types for AMDGPU
+enum {
+#include "ELFRelocs/AMDGPU.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.
Index: include/llvm/Support/ELFRelocs/AMDGPU.def
===================================================================
--- /dev/null
+++ include/llvm/Support/ELFRelocs/AMDGPU.def
@@ -0,0 +1,7 @@
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AMDGPU_NONE,          0)
+ELF_RELOC(R_AMDGPU_ABS32_LO,      1)
+ELF_RELOC(R_AMDGPU_ABS32_HI,      2)
Index: lib/Object/ELF.cpp
===================================================================
--- lib/Object/ELF.cpp
+++ lib/Object/ELF.cpp
@@ -105,6 +105,13 @@
       break;
     }
     break;
+  case ELF::EM_AMDGPU:
+    switch (Type) {
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    default:
+      break;
+    }
+    break;
   default:
     break;
   }
Index: lib/ObjectYAML/ELFYAML.cpp
===================================================================
--- lib/ObjectYAML/ELFYAML.cpp
+++ lib/ObjectYAML/ELFYAML.cpp
@@ -531,6 +531,9 @@
   case ELF::EM_LANAI:
 #include "llvm/Support/ELFRelocs/Lanai.def"
     break;
+  case ELF::EM_AMDGPU:
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -21,10 +21,7 @@
   AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend);
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                        const MCFixup &Fixup, bool IsPCRel) const override {
-    return Fixup.getKind();
-  }
-
+                        const MCFixup &Fixup, bool IsPCRel) const override;
 };
 
 
@@ -37,6 +34,24 @@
                             ELF::EM_AMDGPU,
                             HasRelocationAddend) { }
 
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
+                                             const MCValue &Target,
+                                             const MCFixup &Fixup,
+                                             bool IsPCRel) const {
+  switch (Fixup.getKind()) {
+  default: break;
+  case FK_Data_4:
+    // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
+    // the scratch buffer.
+    if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0")
+      return ELF::R_AMDGPU_ABS32_LO;
+    if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
+      return ELF::R_AMDGPU_ABS32_HI;
+  }
+
+  llvm_unreachable("unhandled relocation type");
+}
+
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,
Index: test/CodeGen/AMDGPU/large-alloca-compute.ll
===================================================================
--- test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -2,9 +2,17 @@
 ; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -relocations | FileCheck --check-prefix=ELF %s
 
 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
 
+; ELF: Relocations [
+; ELF:  .rel.text {
+; ELF: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+; ELF: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+; ELF:  }
+; ELF: ]
+
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0