Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -1479,6 +1479,7 @@
 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
+def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>;
 
 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
 
Index: lib/Target/AMDGPU/VIInstructions.td
===================================================================
--- lib/Target/AMDGPU/VIInstructions.td
+++ lib/Target/AMDGPU/VIInstructions.td
@@ -75,6 +75,12 @@
 } // End isCommutable = 1
 defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;
 
+//===----------------------------------------------------------------------===//
+// VOP3 Instructions
+//===----------------------------------------------------------------------===//
+let isCommutable = 1 in {
+    defm V_MAD_I16 : VOP3Inst <vop3<0, 0x34>, "v_mad_i16", VOP_I16_I16_I16_I16>;
+}
 } // let DisableSIDecoder = 1
 
 // Aliases to simplify matching of floating-point instructions that
@@ -272,6 +278,12 @@
     (V_CVT_F16_F32_e32 $src)
 >;
 
+def : Pat<
+    (add (mul i16:$src0, i16:$src1), i16:$src2),
+    (V_MAD_I16 i16:$src0, i16:$src1, i16:$src2)
+>;
+
+defm : Arithmetic_i16_Pats<mul, V_MUL_F16_e32>;
 
 defm : Arithmetic_i16_Pats<add, V_ADD_U16_e32>;
 defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e32>;