Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp @@ -3927,26 +3927,6 @@ } } -/// \brief Return true if the condition is an unsigned comparison operation. -static bool isX86CCUnsigned(unsigned X86CC) { - switch (X86CC) { - default: - llvm_unreachable("Invalid integer condition!"); - case X86::COND_E: - case X86::COND_NE: - case X86::COND_B: - case X86::COND_A: - case X86::COND_BE: - case X86::COND_AE: - return true; - case X86::COND_G: - case X86::COND_GE: - case X86::COND_L: - case X86::COND_LE: - return false; - } -} - static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) { switch (SetCCOpcode) { default: llvm_unreachable("Invalid integer condition!"); @@ -14766,18 +14746,6 @@ if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { - // Do the comparison at i32 if it's smaller, besides the Atom case. - // This avoids subregister aliasing issues. Keep the smaller reference - // if we're optimizing for size, however, as that'll allow better folding - // of memory operations. - if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 && - !DAG.getMachineFunction().getFunction()->optForMinSize() && - !Subtarget.isAtom()) { - unsigned ExtendOp = - isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; - Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0); - Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1); - } // Use SUB instead of CMP to enable CSE between SUB and CMP. SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Index: llvm/trunk/test/CodeGen/X86/3addr-16bit.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/3addr-16bit.ll +++ llvm/trunk/test/CodeGen/X86/3addr-16bit.ll @@ -12,7 +12,7 @@ ; 64BIT-LABEL: t1: ; 64BIT-NOT: movw %si, %ax -; 64BIT: leal 1(%rsi), %eax +; 64BIT: movl %esi, %eax %0 = icmp eq i16 %k, %c ; [#uses=1] %1 = add i16 %k, 1 ; [#uses=3] br i1 %0, label %bb, label %bb1 @@ -34,7 +34,7 @@ ; 64BIT-LABEL: t2: ; 64BIT-NOT: movw %si, %ax -; 64BIT: leal -1(%rsi), %eax +; 64BIT: movl %esi, %eax ; 64BIT: movzwl %ax %0 = icmp eq i16 %k, %c ; [#uses=1] %1 = add i16 %k, -1 ; [#uses=3] @@ -59,7 +59,7 @@ ; 64BIT-LABEL: t3: ; 64BIT-NOT: movw %si, %ax -; 64BIT: leal 2(%rsi), %eax +; 64BIT: movl %esi, %eax %0 = add i16 %k, 2 ; [#uses=3] %1 = icmp eq i16 %k, %c ; [#uses=1] br i1 %1, label %bb, label %bb1 @@ -82,7 +82,7 @@ ; 64BIT-LABEL: t4: ; 64BIT-NOT: movw %si, %ax -; 64BIT: leal (%rsi,%rdi), %eax +; 64BIT: movl %esi, %eax %0 = add i16 %k, %c ; [#uses=3] %1 = icmp eq i16 %k, %c ; [#uses=1] br i1 %1, label %bb, label %bb1 Index: llvm/trunk/test/CodeGen/X86/atomic16.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/atomic16.ll +++ llvm/trunk/test/CodeGen/X86/atomic16.ll @@ -154,17 +154,19 @@ } define void @atomic_fetch_max16(i16 %x) nounwind { +; X64-LABEL: atomic_fetch_max16 +; X32-LABEL: atomic_fetch_max16 %t1 = atomicrmw max i16* @sc16, i16 %x acquire -; X64: movswl -; X64: movswl -; X64: subl +; X64: movw +; X64: movw +; X64: subw ; X64: cmov ; X64: lock ; X64: cmpxchgw -; X32: movswl -; X32: movswl -; X32: subl +; X32: movw +; X32: movw +; X32: subw ; X32: cmov ; X32: lock ; X32: cmpxchgw @@ -174,17 +176,19 @@ } define void @atomic_fetch_min16(i16 %x) nounwind { +; X64-LABEL: atomic_fetch_min16 +; X32-LABEL: atomic_fetch_min16 %t1 = atomicrmw min i16* @sc16, i16 %x acquire -; X64: movswl -; X64: movswl -; X64: subl +; X64: movw +; X64: movw +; X64: subw ; X64: cmov ; X64: lock ; X64: cmpxchgw -; X32: movswl -; X32: movswl -; X32: subl +; X32: movw +; X32: movw +; X32: subw ; X32: cmov ; X32: lock ; X32: cmpxchgw @@ -194,17 +198,19 @@ } define void @atomic_fetch_umax16(i16 %x) nounwind { +; X64-LABEL: atomic_fetch_umax16 +; X32-LABEL: atomic_fetch_umax16 %t1 = atomicrmw umax i16* @sc16, i16 %x acquire -; X64: movzwl -; X64: movzwl -; X64: subl +; X64: movw +; X64: movw +; X64: subw ; X64: cmov ; X64: lock ; X64: cmpxchgw -; X32: movzwl -; X32: movzwl -; X32: subl +; X32: movw +; X32: movw +; X32: subw ; X32: cmov ; X32: lock ; X32: cmpxchgw @@ -214,17 +220,19 @@ } define void @atomic_fetch_umin16(i16 %x) nounwind { +; X64-LABEL: atomic_fetch_umin16 +; X32-LABEL: atomic_fetch_umin16 %t1 = atomicrmw umin i16* @sc16, i16 %x acquire -; X64: movzwl -; X64: movzwl -; X64: subl +; X64: movw +; X64: movw +; X64: subw ; X64: cmov ; X64: lock ; X64: cmpxchgw -; X32: movzwl -; X32: movzwl -; X32: subl +; X32: movw +; X32: movw +; X32: subw ; X32: cmov ; X32: lock ; X32: cmpxchgw Index: llvm/trunk/test/CodeGen/X86/atomic8.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/atomic8.ll +++ llvm/trunk/test/CodeGen/X86/atomic8.ll @@ -157,15 +157,15 @@ ; X64-LABEL: atomic_fetch_max8: ; X32-LABEL: atomic_fetch_max8: %t1 = atomicrmw max i8* @sc8, i8 %x acquire -; X64: movsbl -; X64: movsbl -; X64: subl +; X64: movb +; X64: movb +; X64: subb ; X64: lock ; X64: cmpxchgb -; X32: movsbl -; X32: movsbl -; X32: subl +; X32: movb +; X32: movb +; X32: subb ; X32: lock ; X32: cmpxchgb ret void @@ -177,15 +177,15 @@ ; X64-LABEL: atomic_fetch_min8: ; X32-LABEL: atomic_fetch_min8: %t1 = atomicrmw min i8* @sc8, i8 %x acquire -; X64: movsbl -; X64: movsbl -; X64: subl +; X64: movb +; X64: movb +; X64: subb ; X64: lock ; X64: cmpxchgb -; X32: movsbl -; X32: movsbl -; X32: subl +; X32: movb +; X32: movb +; X32: subb ; X32: lock ; X32: cmpxchgb ret void @@ -197,15 +197,15 @@ ; X64-LABEL: atomic_fetch_umax8: ; X32-LABEL: atomic_fetch_umax8: %t1 = atomicrmw umax i8* @sc8, i8 %x acquire -; X64: movzbl -; X64: movzbl -; X64: subl +; X64: movb +; X64: movb +; X64: subb ; X64: lock ; X64: cmpxchgb -; X32: movzbl -; X32: movzbl -; X32: subl +; X32: movb +; X32: movb +; X32: subb ; X32: lock ; X32: cmpxchgb ret void @@ -217,15 +217,15 @@ ; X64-LABEL: atomic_fetch_umin8: ; X32-LABEL: atomic_fetch_umin8: %t1 = atomicrmw umin i8* @sc8, i8 %x acquire -; X64: movzbl -; X64: movzbl -; X64: subl +; X64: movb +; X64: movb +; X64: subb ; X64: lock ; X64: cmpxchgb -; X32: movzbl -; X32: movzbl -; X32: subl +; X32: movb +; X32: movb +; X32: subb ; X32: lock ; X32: cmpxchgb ret void Index: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll +++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll @@ -35,6 +35,6 @@ %conv = zext i1 %cmp to i32 ret i32 %conv ; CHECK-LABEL: test3: -; CHECK: cmpl $2 +; CHECK: cmpb $2 ; CHECK: ret } Index: llvm/trunk/test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll +++ llvm/trunk/test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll @@ -67,7 +67,7 @@ ; CHECK-NEXT: .byte 1 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 -; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long 1 ; FunctionInfo[0] = Index: llvm/trunk/test/CodeGen/X86/memcmp.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/memcmp.ll +++ llvm/trunk/test/CodeGen/X86/memcmp.ll @@ -23,8 +23,7 @@ ret void ; CHECK-LABEL: memcmp2: ; CHECK: movzwl -; CHECK-NEXT: movzwl -; CHECK-NEXT: cmpl +; CHECK-NEXT: cmpw ; NOBUILTIN-LABEL: memcmp2: ; NOBUILTIN: callq } @@ -42,8 +41,7 @@ return: ; preds = %entry ret void ; CHECK-LABEL: memcmp2a: -; CHECK: movzwl -; CHECK-NEXT: cmpl $28527, +; CHECK: cmpw $28527, (% } Index: llvm/trunk/test/CodeGen/X86/pr5145.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/pr5145.ll +++ llvm/trunk/test/CodeGen/X86/pr5145.ll @@ -5,26 +5,26 @@ ; CHECK: atomic_maxmin_i8 %1 = atomicrmw max i8* @sc8, i8 5 acquire ; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]: -; CHECK: movsbl -; CHECK: cmpl +; CHECK: cmpb +; CHECK: jg ; CHECK: lock cmpxchgb ; CHECK: jne [[LABEL1]] %2 = atomicrmw min i8* @sc8, i8 6 acquire ; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]: -; CHECK: movsbl -; CHECK: cmpl +; CHECK: cmpb +; CHECK: jl ; CHECK: lock cmpxchgb ; CHECK: jne [[LABEL3]] %3 = atomicrmw umax i8* @sc8, i8 7 acquire ; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]: -; CHECK: movzbl -; CHECK: cmpl +; CHECK: cmpb +; CHECK: ja ; CHECK: lock cmpxchgb ; CHECK: jne [[LABEL5]] %4 = atomicrmw umin i8* @sc8, i8 8 acquire ; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]: -; CHECK: movzbl -; CHECK: cmpl +; CHECK: cmpb +; CHECK: jb ; CHECK: lock cmpxchgb ; CHECK: jne [[LABEL7]] ret void Index: llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll +++ llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -520,8 +520,7 @@ ; CHECK: testq %rdi, %rdi ; CHECK-NEXT: je [[CLEANUP:LBB[0-9_]+]] ; -; CHECK: movzwl (%rdi), [[BF_LOAD:%e[a-z]+]] -; CHECK-NEXT: cmpl $66, [[BF_LOAD]] +; CHECK: cmpw $66, (%rdi) ; CHECK-NEXT: jne [[CLEANUP]] ; ; CHECK: movq 8(%rdi), %rdi