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Differential D21064

[LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions
ClosedPublic

Authored by nitesh.jain on Jun 7 2016, 3:53 AM.

Details

Reviewers
bhushan
clayborg
jaydeep
Summary

This patch contains 2 changes:

  1. Corrected target address calculation of compact branch instructions to reflect changes in disassembler (http://reviews.llvm.org/D17540).
  2. Added emulation for (missing) 'Addiu' instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

nitesh.jain updated this revision to Diff 59856.Jun 7 2016, 3:53 AM
nitesh.jain retitled this revision from to [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions.
nitesh.jain updated this object.
nitesh.jain added reviewers: clayborg, bhushan, jaydeep.
nitesh.jain set the repository for this revision to rL LLVM.
nitesh.jain added subscribers: slthakur, mohit.bhakkad, lldb-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptJun 7 2016, 3:53 AM
jaydeep accepted this revision.Jun 8 2016, 9:15 PM
jaydeep edited edge metadata.

Looks good to me.

This revision is now accepted and ready to land.Jun 8 2016, 9:15 PM
bhushan accepted this revision.Jun 9 2016, 3:56 AM
bhushan edited edge metadata.

Looks good.

clayborg accepted this revision.Jun 20 2016, 5:19 PM
clayborg edited edge metadata.
slthakur closed this revision.Jun 22 2016, 11:57 PM

Committed in rL273535

sdardis added a comment.Jun 23 2016, 2:28 AM

You also need to emulate dsubu and subu as the MIPS LLVM backend will generate them in certain cases.

nitesh.jain added a comment.Jun 23 2016, 2:30 AM
In D21064#465410, @sdardis wrote:

You also need to emulate dsubu and subu as the MIPS LLVM backend will generate them in certain cases.

Thanks will emulate them too.

Revision Contents

PathSize
source/
Plugins/
Instruction/
MIPS/
32 lines
MIPS64/
33 lines

Diff 59856

source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

Show First 20 Lines • Show All 1,476 Lines • ▼ Show 20 LinesEmulateInstructionMIPS::Emulate_BXX_3ops_C (llvm::MCInst& insn)
rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success);
if (!success) if (!success)
return false; return false;
if (!strcasecmp (op_name, "BEQC")) if (!strcasecmp (op_name, "BEQC"))
{ {
if (rs_val == rt_val) if (rs_val == rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNEC")) else if (!strcasecmp (op_name, "BNEC"))
{ {
if (rs_val != rt_val) if (rs_val != rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLTC")) else if (!strcasecmp (op_name, "BLTC"))
{ {
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEC")) else if (!strcasecmp (op_name, "BGEC"))
{ {
if (rs_val >= rt_val) if (rs_val >= rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLTUC")) else if (!strcasecmp (op_name, "BLTUC"))
{ {
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEUC")) else if (!strcasecmp (op_name, "BGEUC"))
{ {
if ((uint32_t)rs_val >= (uint32_t)rt_val) if ((uint32_t)rs_val >= (uint32_t)rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BOVC")) else if (!strcasecmp (op_name, "BOVC"))
{ {
if (IsAdd64bitOverflow (rs_val, rt_val)) if (IsAdd64bitOverflow (rs_val, rt_val))
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNVC")) else if (!strcasecmp (op_name, "BNVC"))
{ {
if (!IsAdd64bitOverflow (rs_val, rt_val)) if (!IsAdd64bitOverflow (rs_val, rt_val))
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset); context.SetImmediate (current_inst_size + offset);
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 LinesEmulateInstructionMIPS::Emulate_BXX_2ops_C (llvm::MCInst& insn)
rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success);
if (!success) if (!success)
return false; return false;
if (!strcasecmp (op_name, "BLTZC")) if (!strcasecmp (op_name, "BLTZC"))
{ {
if (rs_val < 0) if (rs_val < 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLEZC")) else if (!strcasecmp (op_name, "BLEZC"))
{ {
if (rs_val <= 0) if (rs_val <= 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEZC")) else if (!strcasecmp (op_name, "BGEZC"))
{ {
if (rs_val >= 0) if (rs_val >= 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGTZC")) else if (!strcasecmp (op_name, "BGTZC"))
{ {
if (rs_val > 0) if (rs_val > 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BEQZC")) else if (!strcasecmp (op_name, "BEQZC"))
{ {
if (rs_val == 0) if (rs_val == 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNEZC")) else if (!strcasecmp (op_name, "BNEZC"))
{ {
if (rs_val != 0) if (rs_val != 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset); context.SetImmediate (current_inst_size + offset);
▲ Show 20 Lines • Show All 304 Lines • ▼ Show 20 LinesEmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn)
* PC = PC + 4 + offset * PC = PC + 4 + offset
*/ */
offset = insn.getOperand(0).getImm(); offset = insn.getOperand(0).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
if (!success) if (!success)
return false; return false;
target = pc + 4 + offset; target = pc + offset;
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target))
return false; return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4))
return false; return false;
Show All 13 LinesEmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn)
* PC = PC + 4 + offset * PC = PC + 4 + offset
*/ */
offset = insn.getOperand(0).getImm(); offset = insn.getOperand(0).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success);
if (!success) if (!success)
return false; return false;
target = pc + 4 + offset; target = pc + offset;
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target))
return false; return false;
return true; return true;
} }
▲ Show 20 Lines • Show All 606 Lines • Show Last 20 Lines

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

Show First 20 Lines • Show All 477 Lines • ▼ Show 20 Lines
{ {
static EmulateInstructionMIPS64::MipsOpcode static EmulateInstructionMIPS64::MipsOpcode
g_opcodes[] = g_opcodes[] =
{ {
//---------------------------------------------------------------------- //----------------------------------------------------------------------
// Prologue/Epilogue instructions // Prologue/Epilogue instructions
//---------------------------------------------------------------------- //----------------------------------------------------------------------
{ "DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "DADDIU rt,rs,immediate" }, { "DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "DADDIU rt,rs,immediate" },
{ "ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "ADDIU rt,rs,immediate" },
{ "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" }, { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" },
{ "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" }, { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" },
//---------------------------------------------------------------------- //----------------------------------------------------------------------
// Load/Store instructions // Load/Store instructions
▲ Show 20 Lines • Show All 567 Lines • ▼ Show 20 LinesEmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn)
* PC = PC + 4 + offset * PC = PC + 4 + offset
*/ */
offset = insn.getOperand(0).getImm(); offset = insn.getOperand(0).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
target = pc + 4 + offset; target = pc + offset;
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4))
return false; return false;
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 LinesEmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn)
* PC = PC + 4 + offset * PC = PC + 4 + offset
*/ */
offset = insn.getOperand(0).getImm(); offset = insn.getOperand(0).getImm();
pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
if (!success) if (!success)
return false; return false;
target = pc + 4 + offset; target = pc + offset;
Context context; Context context;
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target))
return false; return false;
return true; return true;
} }
Show All 32 LinesEmulateInstructionMIPS64::Emulate_BXX_3ops_C (llvm::MCInst& insn)
rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
if (!success) if (!success)
return false; return false;
if (!strcasecmp (op_name, "BEQC")) if (!strcasecmp (op_name, "BEQC"))
{ {
if (rs_val == rt_val) if (rs_val == rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNEC")) else if (!strcasecmp (op_name, "BNEC"))
{ {
if (rs_val != rt_val) if (rs_val != rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLTC")) else if (!strcasecmp (op_name, "BLTC"))
{ {
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEC")) else if (!strcasecmp (op_name, "BGEC"))
{ {
if (rs_val >= rt_val) if (rs_val >= rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLTUC")) else if (!strcasecmp (op_name, "BLTUC"))
{ {
if (rs_val < rt_val) if (rs_val < rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEUC")) else if (!strcasecmp (op_name, "BGEUC"))
{ {
if ((uint32_t)rs_val >= (uint32_t)rt_val) if ((uint32_t)rs_val >= (uint32_t)rt_val)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BOVC")) else if (!strcasecmp (op_name, "BOVC"))
{ {
if (IsAdd64bitOverflow (rs_val, rt_val)) if (IsAdd64bitOverflow (rs_val, rt_val))
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNVC")) else if (!strcasecmp (op_name, "BNVC"))
{ {
if (!IsAdd64bitOverflow (rs_val, rt_val)) if (!IsAdd64bitOverflow (rs_val, rt_val))
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset); context.SetImmediate (current_inst_size + offset);
Show All 26 LinesEmulateInstructionMIPS64::Emulate_BXX_2ops_C (llvm::MCInst& insn)
rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
if (!success) if (!success)
return false; return false;
if (!strcasecmp (op_name, "BLTZC")) if (!strcasecmp (op_name, "BLTZC"))
{ {
if (rs_val < 0) if (rs_val < 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BLEZC")) else if (!strcasecmp (op_name, "BLEZC"))
{ {
if (rs_val <= 0) if (rs_val <= 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGEZC")) else if (!strcasecmp (op_name, "BGEZC"))
{ {
if (rs_val >= 0) if (rs_val >= 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BGTZC")) else if (!strcasecmp (op_name, "BGTZC"))
{ {
if (rs_val > 0) if (rs_val > 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BEQZC")) else if (!strcasecmp (op_name, "BEQZC"))
{ {
if (rs_val == 0) if (rs_val == 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
else if (!strcasecmp (op_name, "BNEZC")) else if (!strcasecmp (op_name, "BNEZC"))
{ {
if (rs_val != 0) if (rs_val != 0)
target = pc + 4 + offset; target = pc + offset;
else else
target = pc + 4; target = pc + 4;
} }
Context context; Context context;
context.type = eContextRelativeBranchImmediate; context.type = eContextRelativeBranchImmediate;
context.SetImmediate (current_inst_size + offset); context.SetImmediate (current_inst_size + offset);
▲ Show 20 Lines • Show All 620 Lines • Show Last 20 Lines