Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -47,7 +47,8 @@
                                                MachineFunction &MF) {
   MachineInstrBuilder MIB(MF, &MI);
   unsigned Mask = MI.getOperand(1).getImm();
-  unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
+  unsigned Flag =
+      IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
 
   if (Mask & 1)
     MIB.addReg(Mips::DSPPos, Flag);
Index: test/CodeGen/Mips/dsp-r1.ll
===================================================================
--- test/CodeGen/Mips/dsp-r1.ll
+++ test/CodeGen/Mips/dsp-r1.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
+; RUN:     FileCheck %s
 
 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
 entry: