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[mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores.
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Authored by dsanders on Jun 7 2016, 2:23 AM.

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Summary

[ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore
lower frameindex nodes such that there is a copy to a CPU16Regs register. This
is now done consistently using a separate addressing mode that does not
permit frameindex nodes.

As part of this I've had to remove an optimization that reduced the number of
instructions needed to work around the lack of sp-relative addresses on [ls][bh]
and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as
a copy of the stack pointer and it's implementation was the root cause of many
of the register vs register class mismatches.

lw/sw can use sp-relative addresses but we ought to ensure that we use the
correct version of lw/sw internally for things like IAS. This is not currently
the case and this change does not fix this. However, this change does clean it
up sufficiently well to fix the machine verifier failures.

Also removed irrelevant functions from stchar.ll.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 59848.Jun 7 2016, 2:23 AM
dsanders retitled this revision from to [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores..
dsanders updated this object.
dsanders added a reviewer: sdardis.
dsanders added a subscriber: llvm-commits.
dsanders updated this revision to Diff 59852.Jun 7 2016, 3:29 AM

Fix MIR test case.

sdardis accepted this revision.Jun 15 2016, 5:25 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jun 15 2016, 5:25 AM
dsanders updated this revision to Diff 60954.Jun 16 2016, 2:41 AM
dsanders edited edge metadata.

Refresh before commit

dsanders closed this revision.Jun 16 2016, 3:27 AM