Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1869,7 +1869,9 @@
     case ISD::FADD:
     case ISD::FDIV:
     case ISD::FMAXNUM:
+    case ISD::FMAXNAN:
     case ISD::FMINNUM:
+    case ISD::FMINNAN:
     case ISD::FMUL:
     case ISD::FPOW:
     case ISD::FREM:
Index: test/CodeGen/ARM/fp16-promote.ll
===================================================================
--- test/CodeGen/ARM/fp16-promote.ll
+++ test/CodeGen/ARM/fp16-promote.ll
@@ -929,4 +929,15 @@
   ret half %r
 }
 
+; CHECK-LABEL: test_f16_fminmaxnan:
+; CHECK: vmin.f32
+; CHECK: vmax.f32
+define half @test_f16_fminmaxnan(half %p) #0 {
+  %cmp1 = fcmp ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
 attributes #0 = { nounwind }
Index: test/CodeGen/ARM/vminmaxnm.ll
===================================================================
--- test/CodeGen/ARM/vminmaxnm.ll
+++ test/CodeGen/ARM/vminmaxnm.ll
@@ -372,6 +372,19 @@
   ret float %cond2
 }
 
+define half @fp-armv8_vminmaxnm_f16_promote(half %p) #0 {
+; CHECK-LABEL: "fp-armv8_vminmaxnm_f16_promote":
+; CHECK-NOT: vcmp
+; CHECK: vminnm.f32
+; CHECK: vmaxnm.f32
+  %cmp1 = fcmp fast ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp fast ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
+
 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone