Index: test/MC/Mips/higher-highest-addressing.s
===================================================================
--- test/MC/Mips/higher-highest-addressing.s
+++ test/MC/Mips/higher-highest-addressing.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
-# RUN:  | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+# RUN:   | llvm-objdump -disassemble - | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
-# RUN:  | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
+# RUN:   | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
 
 
 # Test that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are created.  By using
Index: test/MC/Mips/micromips-el-fixup-data.s
===================================================================
--- test/MC/Mips/micromips-el-fixup-data.s
+++ test/MC/Mips/micromips-el-fixup-data.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 \
 # RUN:   -mattr=+micromips 2>&1 -filetype=obj > %t.o
-# RUN: llvm-objdump %t.o -triple mipsel -mattr=+micromips -d | FileCheck %s
+# RUN: llvm-objdump %t.o -mattr=+micromips -d | FileCheck %s
 
 # Check that fixup data is written in the microMIPS specific little endian
 # byte order.
Index: test/MC/Mips/mips64extins.ll
===================================================================
--- test/MC/Mips/mips64extins.ll
+++ test/MC/Mips/mips64extins.ll
@@ -1,6 +1,5 @@
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
-; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
-; RUN: | FileCheck %s
+; RUN:   | llvm-objdump -disassemble -mattr +mips64r2 - | FileCheck %s
 
 define i64 @dext(i64 %i) nounwind readnone {
 entry:
Index: test/MC/Mips/mips64shift.ll
===================================================================
--- test/MC/Mips/mips64shift.ll
+++ test/MC/Mips/mips64shift.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
-; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s 
+; RUN:   | llvm-objdump -disassemble - | FileCheck %s
 
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
-; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s 
+; RUN:   | llvm-objdump -disassemble - | FileCheck %s
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
Index: test/MC/Mips/nacl-mask.s
===================================================================
--- test/MC/Mips/nacl-mask.s
+++ test/MC/Mips/nacl-mask.s
@@ -1,6 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
-# RUN:  | llvm-objdump -triple mipsel -disassemble -no-show-raw-insn - \
-# RUN:  | FileCheck %s
+# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # This test tests that address-masking sandboxing is added when given assembly
 # input.
Index: test/MC/Mips/sext_64_32.ll
===================================================================
--- test/MC/Mips/sext_64_32.ll
+++ test/MC/Mips/sext_64_32.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
+; RUN:   llvm-objdump -disassemble - | FileCheck %s
 
 ; Sign extend from 32 to 64 was creating nonsense opcodes
 
Index: test/Object/Mips/feature.test
===================================================================
--- test/Object/Mips/feature.test
+++ test/Object/Mips/feature.test
@@ -1,5 +1,5 @@
-RUN: llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 %p/../Inputs/dext-test.elf-mips64r2 \
-RUN: | FileCheck %s
+RUN: llvm-objdump -disassemble -mattr +mips64r2 %p/../Inputs/dext-test.elf-mips64r2 \
+RUN:   | FileCheck %s
 
 CHECK: Disassembly of section .text:
 CHECK: dext: