Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -186,8 +186,8 @@ class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>; class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>; class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>; -class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>; -class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>; +class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>; +class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>; class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>; class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>; @@ -844,31 +844,31 @@ ISA_MICROMIPS32R6; def CMP_UN_#NAME : POOL32F_CMP_FM< !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>, - CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_EQ_#NAME : POOL32F_CMP_FM< !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>, - CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_UEQ_#NAME : POOL32F_CMP_FM< !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>, - CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_LT_#NAME : POOL32F_CMP_FM< !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>, - CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_ULT_#NAME : POOL32F_CMP_FM< !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>, - CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_LE_#NAME : POOL32F_CMP_FM< !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>, - CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_ULE_#NAME : POOL32F_CMP_FM< !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>, - CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel, + CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6; def CMP_SAF_#NAME : POOL32F_CMP_FM< !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>, @@ -974,8 +974,8 @@ class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; -class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; -class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; +class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; +class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; @@ -1478,15 +1478,15 @@ ISA_MICROMIPS32R6; def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC, ISA_MICROMIPS32R6; -def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6; -def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6; -def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC, +def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6; +def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6; +def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC, ISA_MICROMIPS32R6; -def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC, +def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC, ISA_MICROMIPS32R6; -def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC, +def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC, ISA_MICROMIPS32R6; -def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC, +def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC, ISA_MICROMIPS32R6; def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1568,3 +1568,20 @@ (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6; def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6; + +def : MipsPat<(select i32:$cond, i32:$t, i32:$f), + (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond), + (SELEQZ_MMR6 i32:$f, i32:$cond))>, + ISA_MICROMIPS32R6; +def : MipsPat<(select i32:$cond, i32:$t, immz), + (SELNEZ_MMR6 i32:$t, i32:$cond)>, + ISA_MICROMIPS32R6; +def : MipsPat<(select i32:$cond, immz, i32:$f), + (SELEQZ_MMR6 i32:$f, i32:$cond)>, + ISA_MICROMIPS32R6; + +defm : SelectInt_Pats, ISA_MICROMIPS32R6; + +defm S_MMR6 : Cmp_Pats, ISA_MICROMIPS32R6; +defm D_MMR6 : Cmp_Pats, ISA_MICROMIPS32R6; Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -523,11 +523,11 @@ string Constraints = "$fd_in = $fd"; } -class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> { +class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>, MipsR6Arch<"sel.d"> { // We must insert a SUBREG_TO_REG around $fd_in bit usesCustomInserter = 1; } -class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>; +class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>, MipsR6Arch<"sel.s">; class SELEQNE_Z_DESC_BASE : MipsR6Arch { @@ -580,10 +580,14 @@ list Pattern = []; } -class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; -class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; -class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; -class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; +class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>, + MipsR6Arch<"seleqz.s">; +class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>, + MipsR6Arch<"seleqz.d">; +class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>, + MipsR6Arch<"selnez.s">; +class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>, + MipsR6Arch<"selnez.d">; class CLASS_RINT_DESC_BASE { dag OutOperandList = (outs FGROpnd:$fd); @@ -799,17 +803,15 @@ def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; } def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; -def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; let AdditionalPredicates = [NotInMicroMips] in { - def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; - def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; -} -def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; -let AdditionalPredicates = [NotInMicroMips] in { - def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; - def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; - def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; - def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; + def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; + def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; + def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; + def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; + def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; } def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; @@ -855,8 +857,10 @@ (NOROp (!cast("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; } -defm S : Cmp_Pats, ISA_MIPS32R6; -defm D : Cmp_Pats, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + defm S : Cmp_Pats, ISA_MIPS32R6; + defm D : Cmp_Pats, ISA_MIPS32R6; +} // i32 selects multiclass SelectInt_Pats; } +let AdditionalPredicates = [NotInMicroMips] in { defm : SelectInt_Pats, ISA_MIPS32R6; @@ -908,3 +913,4 @@ def : MipsPat<(select i32:$cond, immz, i32:$f), (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; +} Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -1071,6 +1071,7 @@ case Mips::DMODU_MM64R6: return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); case Mips::SEL_D: + case Mips::SEL_D_MMR6: return emitSEL_D(MI, BB); case Mips::PseudoSELECT_I: Index: test/CodeGen/Mips/llvm-ir/select-dbl.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/select-dbl.ll +++ test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -13,7 +13,7 @@ ; RUN: -check-prefix=ALL -check-prefix=CMOV \ ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 +; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ @@ -27,7 +27,11 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 +; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { entry: @@ -71,6 +75,13 @@ ; SEL-64: mtc1 $4, $f0 ; SEL-64: sel.d $f0, $f14, $f13 + + ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]] + ; MM32R3: mthc1 $6, $[[F0]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: ldc1 $f0, 16($sp) + ; MM32R3: movn.d $f0, $[[F0]], $[[T0]] + %r = select i1 %s, double %x, double %y ret double %r } @@ -112,6 +123,12 @@ ; SEL-64: mtc1 $6, $f0 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: lw $[[T0:[0-9]+]], 16($sp) + ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1 + ; MM32R3: movn.d $f14, $f12, $[[T1]] + ; MM32R3: mov.d $f0, $f14 + %r = select i1 %s, double %x, double %y ret double %r } @@ -143,6 +160,11 @@ ; SEL-64: cmp.lt.d $f0, $f12, $f13 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.olt.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp olt double %x, %y %r = select i1 %s, double %x, double %y ret double %r @@ -175,6 +197,11 @@ ; SEL-64: cmp.le.d $f0, $f12, $f13 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ole.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp ole double %x, %y %r = select i1 %s, double %x, double %y ret double %r @@ -207,6 +234,11 @@ ; SEL-64: cmp.lt.d $f0, $f13, $f12 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ule.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp ogt double %x, %y %r = select i1 %s, double %x, double %y ret double %r @@ -239,6 +271,11 @@ ; SEL-64: cmp.le.d $f0, $f13, $f12 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ult.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp oge double %x, %y %r = select i1 %s, double %x, double %y ret double %r @@ -271,6 +308,11 @@ ; SEL-64: cmp.eq.d $f0, $f12, $f13 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.eq.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp oeq double %x, %y %r = select i1 %s, double %x, double %y ret double %r @@ -296,7 +338,8 @@ ; SEL-32: cmp.ueq.d $f0, $f12, $f14 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] + ; 32R6: not $[[T0]], $[[T0]] + ; MM32R6: nor $[[T0]], $[[T0]], $zero ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 ; SEL-32: sel.d $f0, $f14, $f12 @@ -309,6 +352,11 @@ ; SEL-64: not $[[T0]], $[[T0]] ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ueq.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + %s = fcmp one double %x, %y %r = select i1 %s, double %x, double %y ret double %r Index: test/CodeGen/Mips/llvm-ir/select-flt.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/select-flt.ll +++ test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -13,7 +13,7 @@ ; RUN: -check-prefix=ALL -check-prefix=CMOV \ ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 +; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ @@ -27,7 +27,11 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 +; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { entry: @@ -60,6 +64,12 @@ ; SEL-64: mtc1 $4, $f0 ; SEL-64: sel.s $f0, $f14, $f13 + + ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]] + ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn.s $f0, $[[F1]], $[[T0]] + %r = select i1 %s, float %x, float %y ret float %r } @@ -91,6 +101,11 @@ ; SEL-64: mtc1 $6, $f0 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1 + ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]] + ; MM32R3: mov.s $f0, $[[F0]] + %r = select i1 %s, float %x, float %y ret float %r } @@ -122,6 +137,11 @@ ; SEL-64: cmp.lt.s $f0, $f12, $f13 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.olt.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp olt float %x, %y %r = select i1 %s, float %x, float %y ret float %r @@ -154,6 +174,11 @@ ; SEL-64: cmp.le.s $f0, $f12, $f13 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ole.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp ole float %x, %y %r = select i1 %s, float %x, float %y ret float %r @@ -186,6 +211,11 @@ ; SEL-64: cmp.lt.s $f0, $f13, $f12 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ule.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp ogt float %x, %y %r = select i1 %s, float %x, float %y ret float %r @@ -218,6 +248,11 @@ ; SEL-64: cmp.le.s $f0, $f13, $f12 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ult.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp oge float %x, %y %r = select i1 %s, float %x, float %y ret float %r @@ -250,6 +285,11 @@ ; SEL-64: cmp.eq.s $f0, $f12, $f13 ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.eq.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp oeq float %x, %y %r = select i1 %s, float %x, float %y ret float %r @@ -275,7 +315,8 @@ ; SEL-32: cmp.ueq.s $f0, $f12, $f14 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] + ; 32R6: not $[[T0]], $[[T0]] + ; MM32R6: nor $[[T0]], $[[T0]], $zero ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 ; SEL-32: sel.s $f0, $f14, $f12 @@ -289,6 +330,10 @@ ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 ; SEL-64: sel.s $f0, $f13, $f12 + ; MM32R3: c.ueq.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + %s = fcmp one float %x, %y %r = select i1 %s, float %x, float %y ret float %r Index: test/CodeGen/Mips/llvm-ir/select-int.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/select-int.ll +++ test/CodeGen/Mips/llvm-ir/select-int.ll @@ -28,6 +28,10 @@ ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32R6 define signext i1 @tst_select_i1_i1(i1 signext %s, i1 signext %x, i1 signext %y) { @@ -50,6 +54,16 @@ ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i1 %x, i1 %y ret i1 %r } @@ -75,6 +89,16 @@ ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i8 %x, i8 %y ret i8 %r } @@ -100,6 +124,16 @@ ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i32 %x, i32 %y ret i32 %r } @@ -157,6 +191,23 @@ ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] ; SEL-64: selnez $[[T0]], $5, $[[T0]] ; SEL-64: or $2, $[[T0]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: lw $2, 16($sp) + ; MM32R3: movn $2, $6, $[[T0]] + ; MM32R3: lw $3, 20($sp) + ; MM32R3: movn $3, $7, $[[T0]] + + ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R6: lw $[[T1:[0-9]+]], 16($sp) + ; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]] + ; MM32R6: or $2, $[[T3]], $[[T2]] + ; MM32R6: lw $[[T4:[0-9]+]], 20($sp) + ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]] + ; MM32R6: or $3, $[[T6]], $[[T5]] + %r = select i1 %s, i64 %x, i64 %y ret i64 %r } @@ -164,47 +215,58 @@ define i8* @tst_select_word_cst(i8* %a, i8* %b) { ; ALL-LABEL: tst_select_word_cst: - ; M2: addiu $1, $zero, -1 - ; M2: xor $1, $5, $1 - ; M2: sltu $1, $zero, $1 - ; M2: bnez $1, $[[BB0:BB[0-9_]+]] + ; M2: addiu $[[T0:[0-9]+]], $zero, -1 + ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]] ; M2: addiu $2, $zero, 0 ; M2: move $2, $4 ; M2: $[[BB0]]: ; M2: jr $ra - ; M3: daddiu $1, $zero, -1 - ; M3: xor $1, $5, $1 - ; M3: sltu $1, $zero, $1 - ; M3: bnez $1, $[[BB0:BB[0-9_]+]] + ; M3: daddiu $[[T0:[0-9]+]], $zero, -1 + ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]] ; M3: daddiu $2, $zero, 0 ; M3: move $2, $4 ; M3: $[[BB0]]: ; M3: jr $ra - ; CMOV-32: addiu $1, $zero, -1 - ; CMOV-32: xor $1, $5, $1 - ; CMOV-32: movn $4, $zero, $1 + ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]] ; CMOV-32: jr $ra - ; CMOV-32: move $2, $4 + ; CMOV-32: move $2, $[[T2]] - ; SEL-32: addiu $1, $zero, -1 - ; SEL-32: xor $1, $5, $1 - ; SEL-32: sltu $1, $zero, $1 + ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; SEL-32: jr $ra - ; SEL-32: seleqz $2, $4, $1 + ; SEL-32: seleqz $2, $4, $[[T2]] - ; CMOV-64: daddiu $1, $zero, -1 - ; CMOV-64: xor $1, $5, $1 - ; CMOV-64: movn $4, $zero, $1 - ; CMOV-64: move $2, $4 + ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]] + ; CMOV-64: move $2, $[[T2]] - ; SEL-64: daddiu $1, $zero, -1 - ; SEL-64: xor $1, $5, $1 - ; SEL-64: sltu $1, $zero, $1 + ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; FIXME: This shift is redundant. - ; SEL-64: sll $1, $1, 0 - ; SEL-64: seleqz $2, $4, $1 + ; SEL-64: sll $[[T2]], $[[T2]], 0 + ; SEL-64: seleqz $2, $4, $[[T2]] + + ; MM32R3: li16 $[[T0:[0-9]+]], -1 + ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: lui $[[T2:[0-9]+]], 0 + ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32R3: move $2, $[[T3]] + + ; MM32R6: li16 $[[T0:[0-9]+]], -1 + ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; MM32R6: seleqz $2, $4, $[[T2]] %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*) %r = select i1 %cmp, i8* %a, i8* null