Index: include/llvm/CodeGen/MachineOperand.h =================================================================== --- include/llvm/CodeGen/MachineOperand.h +++ include/llvm/CodeGen/MachineOperand.h @@ -142,8 +142,8 @@ /// MO_Register: Register number. /// OffsetedInfo: Low bits of offset. union { - unsigned RegNo; // For MO_Register. - unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. + unsigned RegNo; // For MO_Register. + unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. } SmallContents; /// ParentMI - This is the instruction that this operand is embedded into. @@ -161,9 +161,9 @@ MCSymbol *Sym; // For MO_MCSymbol. unsigned CFIIndex; // For MO_CFI. - struct { // For MO_Register. + struct { // For MO_Register. // Register number is in SmallContents.RegNo. - MachineOperand *Prev; // Access list for register. See MRI. + MachineOperand *Prev; // Access list for register. See MRI. MachineOperand *Next; } Reg; @@ -171,26 +171,25 @@ /// this represent the object as with an optional offset from it. struct { union { - int Index; // For MO_*Index - The index itself. - const char *SymbolName; // For MO_ExternalSymbol. - const GlobalValue *GV; // For MO_GlobalAddress. - const BlockAddress *BA; // For MO_BlockAddress. + int Index; // For MO_*Index - The index itself. + const char *SymbolName; // For MO_ExternalSymbol. + const GlobalValue *GV; // For MO_GlobalAddress. + const BlockAddress *BA; // For MO_BlockAddress. } Val; // Low bits of offset are in SmallContents.OffsetLo. - int OffsetHi; // An offset from the object, high 32 bits. + int OffsetHi; // An offset from the object, high 32 bits. } OffsetedInfo; } Contents; explicit MachineOperand(MachineOperandType K) - : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {} + : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {} + public: /// getType - Returns the MachineOperandType for this operand. /// MachineOperandType getType() const { return (MachineOperandType)OpKind; } - unsigned getTargetFlags() const { - return isReg() ? 0 : SubReg_TargetFlags; - } + unsigned getTargetFlags() const { return isReg() ? 0 : SubReg_TargetFlags; } void setTargetFlags(unsigned F) { assert(!isReg() && "Register operands can't have target flags"); SubReg_TargetFlags = F; @@ -202,7 +201,6 @@ assert((SubReg_TargetFlags & F) && "Target flags out of range"); } - /// getParent - Return the instruction that this operand belongs to. /// MachineInstr *getParent() { return ParentMI; } @@ -355,13 +353,13 @@ /// using TargetRegisterInfo to compose the subreg indices if necessary. /// Reg must be a virtual register, SubIdx can be 0. /// - void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); + void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &); /// substPhysReg - Substitute the current register with the physical register /// Reg, taking any existing SubReg into account. For instance, /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. /// - void substPhysReg(unsigned Reg, const TargetRegisterInfo&); + void substPhysReg(unsigned Reg, const TargetRegisterInfo &); void setIsUse(bool Val = true) { setIsDef(!Val); } @@ -480,7 +478,7 @@ /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. bool clobbersPhysReg(unsigned PhysReg) const { - return clobbersPhysReg(getRegMask(), PhysReg); + return clobbersPhysReg(getRegMask(), PhysReg); } /// getRegMask - Returns a bit mask of registers preserved by this RegMask @@ -534,6 +532,11 @@ Contents.MBB = MBB; } + void setRegMask(const uint32_t *RegMaskPtr) { + assert(isRegMask() && "Wrong MachineOperand mutator"); + Contents.RegMask = RegMaskPtr; + } + //===--------------------------------------------------------------------===// // Other methods. //===--------------------------------------------------------------------===// @@ -598,8 +601,7 @@ bool isKill = false, bool isDead = false, bool isUndef = false, bool isEarlyClobber = false, - unsigned SubReg = 0, - bool isDebug = false, + unsigned SubReg = 0, bool isDebug = false, bool isInternalRead = false) { assert(!(isDead && !isDef) && "Dead flag on non-def"); assert(!(isKill && isDef) && "Kill flag on def"); @@ -647,8 +649,7 @@ Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateJTI(unsigned Idx, - unsigned char TargetFlags = 0) { + static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_JumpTableIndex); Op.setIndex(Idx); Op.setTargetFlags(TargetFlags); @@ -725,6 +726,7 @@ friend class MachineInstr; friend class MachineRegisterInfo; + private: void removeRegFromUses(); @@ -741,14 +743,14 @@ } }; -inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { +inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) { MO.print(OS, nullptr); return OS; } - // See friend declaration above. This additional declaration is required in - // order to compile LLVM with IBM xlC compiler. - hash_code hash_value(const MachineOperand &MO); +// See friend declaration above. This additional declaration is required in +// order to compile LLVM with IBM xlC compiler. +hash_code hash_value(const MachineOperand &MO); } // End llvm namespace #endif Index: include/llvm/CodeGen/Passes.h =================================================================== --- include/llvm/CodeGen/Passes.h +++ include/llvm/CodeGen/Passes.h @@ -33,329 +33,333 @@ /// List of target independent CodeGen pass IDs. namespace llvm { - FunctionPass *createAtomicExpandPass(const TargetMachine *TM); +FunctionPass *createAtomicExpandPass(const TargetMachine *TM); - /// createUnreachableBlockEliminationPass - The LLVM code generator does not - /// work well with unreachable basic blocks (what live ranges make sense for a - /// block that cannot be reached?). As such, a code generator should either - /// not instruction select unreachable blocks, or run this pass as its - /// last LLVM modifying pass to clean up blocks that are not reachable from - /// the entry block. - FunctionPass *createUnreachableBlockEliminationPass(); +/// createUnreachableBlockEliminationPass - The LLVM code generator does not +/// work well with unreachable basic blocks (what live ranges make sense for a +/// block that cannot be reached?). As such, a code generator should either +/// not instruction select unreachable blocks, or run this pass as its +/// last LLVM modifying pass to clean up blocks that are not reachable from +/// the entry block. +FunctionPass *createUnreachableBlockEliminationPass(); - /// MachineFunctionPrinter pass - This pass prints out the machine function to - /// the given stream as a debugging tool. - MachineFunctionPass * - createMachineFunctionPrinterPass(raw_ostream &OS, - const std::string &Banner =""); +/// MachineFunctionPrinter pass - This pass prints out the machine function to +/// the given stream as a debugging tool. +MachineFunctionPass * +createMachineFunctionPrinterPass(raw_ostream &OS, + const std::string &Banner = ""); - /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream - /// using the MIR serialization format. - MachineFunctionPass *createPrintMIRPass(raw_ostream &OS); +/// MIRPrinting pass - this pass prints out the LLVM IR into the given stream +/// using the MIR serialization format. +MachineFunctionPass *createPrintMIRPass(raw_ostream &OS); - /// createCodeGenPreparePass - Transform the code to expose more pattern - /// matching during instruction selection. - FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr); +/// createCodeGenPreparePass - Transform the code to expose more pattern +/// matching during instruction selection. +FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr); - /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg - /// load-linked/store-conditional loops. - extern char &AtomicExpandID; +/// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg +/// load-linked/store-conditional loops. +extern char &AtomicExpandID; - /// MachineLoopInfo - This pass is a loop analysis pass. - extern char &MachineLoopInfoID; +/// MachineLoopInfo - This pass is a loop analysis pass. +extern char &MachineLoopInfoID; - /// MachineDominators - This pass is a machine dominators analysis pass. - extern char &MachineDominatorsID; +/// MachineDominators - This pass is a machine dominators analysis pass. +extern char &MachineDominatorsID; /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass. - extern char &MachineDominanceFrontierID; +extern char &MachineDominanceFrontierID; - /// EdgeBundles analysis - Bundle machine CFG edges. - extern char &EdgeBundlesID; +/// EdgeBundles analysis - Bundle machine CFG edges. +extern char &EdgeBundlesID; - /// LiveVariables pass - This pass computes the set of blocks in which each - /// variable is life and sets machine operand kill flags. - extern char &LiveVariablesID; +/// LiveVariables pass - This pass computes the set of blocks in which each +/// variable is life and sets machine operand kill flags. +extern char &LiveVariablesID; - /// PHIElimination - This pass eliminates machine instruction PHI nodes - /// by inserting copy instructions. This destroys SSA information, but is the - /// desired input for some register allocators. This pass is "required" by - /// these register allocator like this: AU.addRequiredID(PHIEliminationID); - extern char &PHIEliminationID; +/// PHIElimination - This pass eliminates machine instruction PHI nodes +/// by inserting copy instructions. This destroys SSA information, but is the +/// desired input for some register allocators. This pass is "required" by +/// these register allocator like this: AU.addRequiredID(PHIEliminationID); +extern char &PHIEliminationID; - /// LiveIntervals - This analysis keeps track of the live ranges of virtual - /// and physical registers. - extern char &LiveIntervalsID; +/// LiveIntervals - This analysis keeps track of the live ranges of virtual +/// and physical registers. +extern char &LiveIntervalsID; - /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. - extern char &LiveStacksID; +/// LiveStacks pass. An analysis keeping track of the liveness of stack slots. +extern char &LiveStacksID; - /// TwoAddressInstruction - This pass reduces two-address instructions to - /// use two operands. This destroys SSA information but it is desired by - /// register allocators. - extern char &TwoAddressInstructionPassID; +/// TwoAddressInstruction - This pass reduces two-address instructions to +/// use two operands. This destroys SSA information but it is desired by +/// register allocators. +extern char &TwoAddressInstructionPassID; - /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. - extern char &ProcessImplicitDefsID; +/// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. +extern char &ProcessImplicitDefsID; - /// RegisterCoalescer - This pass merges live ranges to eliminate copies. - extern char &RegisterCoalescerID; +/// RegisterCoalescer - This pass merges live ranges to eliminate copies. +extern char &RegisterCoalescerID; - /// MachineScheduler - This pass schedules machine instructions. - extern char &MachineSchedulerID; +/// MachineScheduler - This pass schedules machine instructions. +extern char &MachineSchedulerID; - /// PostMachineScheduler - This pass schedules machine instructions postRA. - extern char &PostMachineSchedulerID; +/// PostMachineScheduler - This pass schedules machine instructions postRA. +extern char &PostMachineSchedulerID; - /// SpillPlacement analysis. Suggest optimal placement of spill code between - /// basic blocks. - extern char &SpillPlacementID; +/// SpillPlacement analysis. Suggest optimal placement of spill code between +/// basic blocks. +extern char &SpillPlacementID; - /// ShrinkWrap pass. Look for the best place to insert save and restore - // instruction and update the MachineFunctionInfo with that information. - extern char &ShrinkWrapID; +/// ShrinkWrap pass. Look for the best place to insert save and restore +// instruction and update the MachineFunctionInfo with that information. +extern char &ShrinkWrapID; - /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as - /// assigned in VirtRegMap. - extern char &VirtRegRewriterID; +/// VirtRegRewriter pass. Rewrite virtual registers to physical registers as +/// assigned in VirtRegMap. +extern char &VirtRegRewriterID; - /// UnreachableMachineBlockElimination - This pass removes unreachable - /// machine basic blocks. - extern char &UnreachableMachineBlockElimID; +/// UnreachableMachineBlockElimination - This pass removes unreachable +/// machine basic blocks. +extern char &UnreachableMachineBlockElimID; - /// DeadMachineInstructionElim - This pass removes dead machine instructions. - extern char &DeadMachineInstructionElimID; +/// DeadMachineInstructionElim - This pass removes dead machine instructions. +extern char &DeadMachineInstructionElimID; - /// This pass adds dead/undef flags after analyzing subregister lanes. - extern char &DetectDeadLanesID; +/// This pass adds dead/undef flags after analyzing subregister lanes. +extern char &DetectDeadLanesID; - /// FastRegisterAllocation Pass - This pass register allocates as fast as - /// possible. It is best suited for debug code where live ranges are short. - /// - FunctionPass *createFastRegisterAllocator(); +/// FastRegisterAllocation Pass - This pass register allocates as fast as +/// possible. It is best suited for debug code where live ranges are short. +/// +FunctionPass *createFastRegisterAllocator(); - /// BasicRegisterAllocation Pass - This pass implements a degenerate global - /// register allocator using the basic regalloc framework. - /// - FunctionPass *createBasicRegisterAllocator(); +/// BasicRegisterAllocation Pass - This pass implements a degenerate global +/// register allocator using the basic regalloc framework. +/// +FunctionPass *createBasicRegisterAllocator(); - /// Greedy register allocation pass - This pass implements a global register - /// allocator for optimized builds. - /// - FunctionPass *createGreedyRegisterAllocator(); +/// Greedy register allocation pass - This pass implements a global register +/// allocator for optimized builds. +/// +FunctionPass *createGreedyRegisterAllocator(); - /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean - /// Quadratic Prograaming (PBQP) based register allocator. - /// - FunctionPass *createDefaultPBQPRegisterAllocator(); +/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean +/// Quadratic Prograaming (PBQP) based register allocator. +/// +FunctionPass *createDefaultPBQPRegisterAllocator(); - /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, - /// and eliminates abstract frame references. - extern char &PrologEpilogCodeInserterID; - MachineFunctionPass *createPrologEpilogInserterPass(const TargetMachine *TM); +/// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, +/// and eliminates abstract frame references. +extern char &PrologEpilogCodeInserterID; +MachineFunctionPass *createPrologEpilogInserterPass(const TargetMachine *TM); - /// ExpandPostRAPseudos - This pass expands pseudo instructions after - /// register allocation. - extern char &ExpandPostRAPseudosID; +/// ExpandPostRAPseudos - This pass expands pseudo instructions after +/// register allocation. +extern char &ExpandPostRAPseudosID; - /// createPostRAHazardRecognizer - This pass runs the post-ra hazard - /// recognizer. - extern char &PostRAHazardRecognizerID; +/// createPostRAHazardRecognizer - This pass runs the post-ra hazard +/// recognizer. +extern char &PostRAHazardRecognizerID; - /// createPostRAScheduler - This pass performs post register allocation - /// scheduling. - extern char &PostRASchedulerID; +/// createPostRAScheduler - This pass performs post register allocation +/// scheduling. +extern char &PostRASchedulerID; - /// BranchFolding - This pass performs machine code CFG based - /// optimizations to delete branches to branches, eliminate branches to - /// successor blocks (creating fall throughs), and eliminating branches over - /// branches. - extern char &BranchFolderPassID; +/// BranchFolding - This pass performs machine code CFG based +/// optimizations to delete branches to branches, eliminate branches to +/// successor blocks (creating fall throughs), and eliminating branches over +/// branches. +extern char &BranchFolderPassID; - /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. - extern char &MachineFunctionPrinterPassID; +/// MachineFunctionPrinterPass - This pass prints out MachineInstr's. +extern char &MachineFunctionPrinterPassID; - /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR - /// serialization format. - extern char &MIRPrintingPassID; +/// MIRPrintingPass - this pass prints out the LLVM IR using the MIR +/// serialization format. +extern char &MIRPrintingPassID; - /// TailDuplicate - Duplicate blocks with unconditional branches - /// into tails of their predecessors. - extern char &TailDuplicateID; +/// TailDuplicate - Duplicate blocks with unconditional branches +/// into tails of their predecessors. +extern char &TailDuplicateID; - /// MachineTraceMetrics - This pass computes critical path and CPU resource - /// usage in an ensemble of traces. - extern char &MachineTraceMetricsID; +/// MachineTraceMetrics - This pass computes critical path and CPU resource +/// usage in an ensemble of traces. +extern char &MachineTraceMetricsID; - /// EarlyIfConverter - This pass performs if-conversion on SSA form by - /// inserting cmov instructions. - extern char &EarlyIfConverterID; +/// EarlyIfConverter - This pass performs if-conversion on SSA form by +/// inserting cmov instructions. +extern char &EarlyIfConverterID; - /// This pass performs instruction combining using trace metrics to estimate - /// critical-path and resource depth. - extern char &MachineCombinerID; +/// This pass performs instruction combining using trace metrics to estimate +/// critical-path and resource depth. +extern char &MachineCombinerID; - /// StackSlotColoring - This pass performs stack coloring and merging. - /// It merges disjoint allocas to reduce the stack size. - extern char &StackColoringID; +/// StackSlotColoring - This pass performs stack coloring and merging. +/// It merges disjoint allocas to reduce the stack size. +extern char &StackColoringID; - /// IfConverter - This pass performs machine code if conversion. - extern char &IfConverterID; - - FunctionPass *createIfConverter(std::function Ftor); - - /// MachineBlockPlacement - This pass places basic blocks based on branch - /// probabilities. - extern char &MachineBlockPlacementID; - - /// MachineBlockPlacementStats - This pass collects statistics about the - /// basic block placement using branch probabilities and block frequency - /// information. - extern char &MachineBlockPlacementStatsID; - - /// GCLowering Pass - Used by gc.root to perform its default lowering - /// operations. - FunctionPass *createGCLoweringPass(); - - /// ShadowStackGCLowering - Implements the custom lowering mechanism - /// used by the shadow stack GC. Only runs on functions which opt in to - /// the shadow stack collector. - FunctionPass *createShadowStackGCLoweringPass(); - - /// GCMachineCodeAnalysis - Target-independent pass to mark safe points - /// in machine code. Must be added very late during code generation, just - /// prior to output, and importantly after all CFG transformations (such as - /// branch folding). - extern char &GCMachineCodeAnalysisID; - - /// Creates a pass to print GC metadata. - /// - FunctionPass *createGCInfoPrinter(raw_ostream &OS); - - /// MachineCSE - This pass performs global CSE on machine instructions. - extern char &MachineCSEID; - - /// ImplicitNullChecks - This pass folds null pointer checks into nearby - /// memory operations. - extern char &ImplicitNullChecksID; - - /// MachineLICM - This pass performs LICM on machine instructions. - extern char &MachineLICMID; - - /// MachineSinking - This pass performs sinking on machine instructions. - extern char &MachineSinkingID; - - /// MachineCopyPropagation - This pass performs copy propagation on - /// machine instructions. - extern char &MachineCopyPropagationID; - - /// PeepholeOptimizer - This pass performs peephole optimizations - - /// like extension and comparison eliminations. - extern char &PeepholeOptimizerID; - - /// OptimizePHIs - This pass optimizes machine instruction PHIs - /// to take advantage of opportunities created during DAG legalization. - extern char &OptimizePHIsID; - - /// StackSlotColoring - This pass performs stack slot coloring. - extern char &StackSlotColoringID; - - /// \brief This pass lays out funclets contiguously. - extern char &FuncletLayoutID; - - /// \brief This pass implements the "patchable-function" attribute. - extern char &PatchableFunctionID; - - /// createStackProtectorPass - This pass adds stack protectors to functions. - /// - FunctionPass *createStackProtectorPass(const TargetMachine *TM); - - /// createMachineVerifierPass - This pass verifies cenerated machine code - /// instructions for correctness. - /// - FunctionPass *createMachineVerifierPass(const std::string& Banner); - - /// createDwarfEHPass - This pass mulches exception handling code into a form - /// adapted to code generation. Required if using dwarf exception handling. - FunctionPass *createDwarfEHPass(const TargetMachine *TM); - - /// createWinEHPass - Prepares personality functions used by MSVC on Windows, - /// in addition to the Itanium LSDA based personalities. - FunctionPass *createWinEHPass(const TargetMachine *TM); - - /// createSjLjEHPreparePass - This pass adapts exception handling code to use - /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. - /// - FunctionPass *createSjLjEHPreparePass(); - - /// LocalStackSlotAllocation - This pass assigns local frame indices to stack - /// slots relative to one another and allocates base registers to access them - /// when it is estimated by the target to be out of range of normal frame - /// pointer or stack pointer index addressing. - extern char &LocalStackSlotAllocationID; - - /// ExpandISelPseudos - This pass expands pseudo-instructions. - extern char &ExpandISelPseudosID; - - /// createExecutionDependencyFixPass - This pass fixes execution time - /// problems with dependent instructions, such as switching execution - /// domains to match. - /// - /// The pass will examine instructions using and defining registers in RC. - /// - FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); - - /// UnpackMachineBundles - This pass unpack machine instruction bundles. - extern char &UnpackMachineBundlesID; - - FunctionPass * - createUnpackMachineBundles(std::function Ftor); - - /// FinalizeMachineBundles - This pass finalize machine instruction - /// bundles (created earlier, e.g. during pre-RA scheduling). - extern char &FinalizeMachineBundlesID; - - /// StackMapLiveness - This pass analyses the register live-out set of - /// stackmap/patchpoint intrinsics and attaches the calculated information to - /// the intrinsic for later emission to the StackMap. - extern char &StackMapLivenessID; - - /// LiveDebugValues pass - extern char &LiveDebugValuesID; - - /// createJumpInstrTables - This pass creates jump-instruction tables. - ModulePass *createJumpInstrTablesPass(); - - /// createForwardControlFlowIntegrityPass - This pass adds control-flow - /// integrity. - ModulePass *createForwardControlFlowIntegrityPass(); - - /// InterleavedAccess Pass - This pass identifies and matches interleaved - /// memory accesses to target specific intrinsics. - /// - FunctionPass *createInterleavedAccessPass(const TargetMachine *TM); - - /// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all - /// TLS variables for the emulated TLS model. - /// - ModulePass *createLowerEmuTLSPass(const TargetMachine *TM); - - /// This pass lowers the @llvm.load.relative intrinsic to instructions. - /// This is unsafe to do earlier because a pass may combine the constant - /// initializer into the load, which may result in an overflowing evaluation. - ModulePass *createPreISelIntrinsicLoweringPass(); - - /// GlobalMerge - This pass merges internal (by default) globals into structs - /// to enable reuse of a base pointer by indexed addressing modes. - /// It can also be configured to focus on size optimizations only. - /// - Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, - bool OnlyOptimizeForSize = false, - bool MergeExternalByDefault = false); - - /// This pass splits the stack into a safe stack and an unsafe stack to - /// protect against stack-based overflow vulnerabilities. - FunctionPass *createSafeStackPass(const TargetMachine *TM = nullptr); +/// IfConverter - This pass performs machine code if conversion. +extern char &IfConverterID; + +FunctionPass *createIfConverter(std::function Ftor); + +/// MachineBlockPlacement - This pass places basic blocks based on branch +/// probabilities. +extern char &MachineBlockPlacementID; + +/// MachineBlockPlacementStats - This pass collects statistics about the +/// basic block placement using branch probabilities and block frequency +/// information. +extern char &MachineBlockPlacementStatsID; + +/// GCLowering Pass - Used by gc.root to perform its default lowering +/// operations. +FunctionPass *createGCLoweringPass(); + +/// ShadowStackGCLowering - Implements the custom lowering mechanism +/// used by the shadow stack GC. Only runs on functions which opt in to +/// the shadow stack collector. +FunctionPass *createShadowStackGCLoweringPass(); + +/// GCMachineCodeAnalysis - Target-independent pass to mark safe points +/// in machine code. Must be added very late during code generation, just +/// prior to output, and importantly after all CFG transformations (such as +/// branch folding). +extern char &GCMachineCodeAnalysisID; + +/// Creates a pass to print GC metadata. +/// +FunctionPass *createGCInfoPrinter(raw_ostream &OS); + +/// MachineCSE - This pass performs global CSE on machine instructions. +extern char &MachineCSEID; + +/// ImplicitNullChecks - This pass folds null pointer checks into nearby +/// memory operations. +extern char &ImplicitNullChecksID; + +/// MachineLICM - This pass performs LICM on machine instructions. +extern char &MachineLICMID; + +/// MachineSinking - This pass performs sinking on machine instructions. +extern char &MachineSinkingID; + +/// MachineCopyPropagation - This pass performs copy propagation on +/// machine instructions. +extern char &MachineCopyPropagationID; + +/// PeepholeOptimizer - This pass performs peephole optimizations - +/// like extension and comparison eliminations. +extern char &PeepholeOptimizerID; + +/// OptimizePHIs - This pass optimizes machine instruction PHIs +/// to take advantage of opportunities created during DAG legalization. +extern char &OptimizePHIsID; + +/// StackSlotColoring - This pass performs stack slot coloring. +extern char &StackSlotColoringID; + +/// \brief This pass lays out funclets contiguously. +extern char &FuncletLayoutID; + +/// \brief This pass implements the "patchable-function" attribute. +extern char &PatchableFunctionID; + +/// createStackProtectorPass - This pass adds stack protectors to functions. +/// +FunctionPass *createStackProtectorPass(const TargetMachine *TM); + +/// createMachineVerifierPass - This pass verifies cenerated machine code +/// instructions for correctness. +/// +FunctionPass *createMachineVerifierPass(const std::string &Banner); + +/// createDwarfEHPass - This pass mulches exception handling code into a form +/// adapted to code generation. Required if using dwarf exception handling. +FunctionPass *createDwarfEHPass(const TargetMachine *TM); + +/// createWinEHPass - Prepares personality functions used by MSVC on Windows, +/// in addition to the Itanium LSDA based personalities. +FunctionPass *createWinEHPass(const TargetMachine *TM); + +/// createSjLjEHPreparePass - This pass adapts exception handling code to use +/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. +/// +FunctionPass *createSjLjEHPreparePass(); + +/// LocalStackSlotAllocation - This pass assigns local frame indices to stack +/// slots relative to one another and allocates base registers to access them +/// when it is estimated by the target to be out of range of normal frame +/// pointer or stack pointer index addressing. +extern char &LocalStackSlotAllocationID; + +/// ExpandISelPseudos - This pass expands pseudo-instructions. +extern char &ExpandISelPseudosID; + +/// createExecutionDependencyFixPass - This pass fixes execution time +/// problems with dependent instructions, such as switching execution +/// domains to match. +/// +/// The pass will examine instructions using and defining registers in RC. +/// +FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); + +/// UnpackMachineBundles - This pass unpack machine instruction bundles. +extern char &UnpackMachineBundlesID; + +FunctionPass * +createUnpackMachineBundles(std::function Ftor); + +/// FinalizeMachineBundles - This pass finalize machine instruction +/// bundles (created earlier, e.g. during pre-RA scheduling). +extern char &FinalizeMachineBundlesID; + +/// StackMapLiveness - This pass analyses the register live-out set of +/// stackmap/patchpoint intrinsics and attaches the calculated information to +/// the intrinsic for later emission to the StackMap. +extern char &StackMapLivenessID; + +/// LiveDebugValues pass +extern char &LiveDebugValuesID; + +/// createJumpInstrTables - This pass creates jump-instruction tables. +ModulePass *createJumpInstrTablesPass(); + +/// createForwardControlFlowIntegrityPass - This pass adds control-flow +/// integrity. +ModulePass *createForwardControlFlowIntegrityPass(); + +/// InterleavedAccess Pass - This pass identifies and matches interleaved +/// memory accesses to target specific intrinsics. +/// +FunctionPass *createInterleavedAccessPass(const TargetMachine *TM); + +/// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all +/// TLS variables for the emulated TLS model. +/// +ModulePass *createLowerEmuTLSPass(const TargetMachine *TM); + +/// This pass lowers the @llvm.load.relative intrinsic to instructions. +/// This is unsafe to do earlier because a pass may combine the constant +/// initializer into the load, which may result in an overflowing evaluation. +ModulePass *createPreISelIntrinsicLoweringPass(); + +/// GlobalMerge - This pass merges internal (by default) globals into structs +/// to enable reuse of a base pointer by indexed addressing modes. +/// It can also be configured to focus on size optimizations only. +/// +Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, + bool OnlyOptimizeForSize = false, + bool MergeExternalByDefault = false); + +/// This pass splits the stack into a safe stack and an unsafe stack to +/// protect against stack-based overflow vulnerabilities. +FunctionPass *createSafeStackPass(const TargetMachine *TM = nullptr); + +/// This pass is executed POST-RA to collect which physical registers are +/// used by given machien function. +FunctionPass *createRegUsageInfoCollector(); } // End llvm namespace /// Target machine pass initializer for passes with dependencies. Use with @@ -364,15 +368,16 @@ /// Target machine pass initializer for passes with dependencies. Use with /// INITIALIZE_TM_PASS_BEGIN. -#define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \ - PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \ - PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \ - PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \ - Registry.registerPass(*PI, true); \ - return PI; \ - } \ - void llvm::initialize##passName##Pass(PassRegistry &Registry) { \ - CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \ +#define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \ + PassInfo *PI = new PassInfo( \ + name, arg, &passName::ID, \ + PassInfo::NormalCtor_t(callDefaultCtor), cfg, analysis, \ + PassInfo::TargetMachineCtor_t(callTargetMachineCtor)); \ + Registry.registerPass(*PI, true); \ + return PI; \ + } \ + void llvm::initialize##passName##Pass(PassRegistry &Registry) { \ + CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \ } /// This initializer registers TargetMachine constructor, so the pass being @@ -380,8 +385,8 @@ /// macro to be together with INITIALIZE_PASS, which is a complete target /// independent initializer, and we don't want to make libScalarOpts depend /// on libCodeGen. -#define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \ - INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \ - INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) +#define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \ + INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \ + INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) #endif Index: include/llvm/CodeGen/PhysicalRegisterUsageInfo.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/PhysicalRegisterUsageInfo.h @@ -0,0 +1,58 @@ +//=- PhysicalRegisterUsageInfo.cpp - Register Usage Informartion Storage -*- C++ +//-*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass is required to get Interprocedural Register Allocation effect. +// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and +// lib/CodeGen/RegUsageInfoCollector.cpp +// +// This pass is simple immutable pass which keeps StringMap of +// function name to RegMask (calculated based on actual register allocation) and +// provides simple API to query this information. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H +#define LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H + +#include "llvm/Pass.h" + +namespace llvm { + +class StringRef; + +class PhysicalRegisterUsageInfo : public ImmutablePass { + virtual void anchor(); + +public: + static char ID; + + PhysicalRegisterUsageInfo() : ImmutablePass(ID) { + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializePhysicalRegisterUsageInfoPass(Registry); + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesAll(); + } + + void storeUpdateRegUsageInfo(StringRef MFName, + std::vector RegMasks); + + const std::vector *getRegUsageInfo(StringRef MFName); + +private: + // A simple map from function name to RegMask + // In RegMask 0 means register used (clobbered) by funciton + // and 1 means content of register will be preserved around function call + StringMap> RegMasks; +}; +} + +#endif \ No newline at end of file Index: include/llvm/InitializePasses.h =================================================================== --- include/llvm/InitializePasses.h +++ include/llvm/InitializePasses.h @@ -21,319 +21,320 @@ /// initializeCore - Initialize all passes linked into the /// TransformUtils library. -void initializeCore(PassRegistry&); +void initializeCore(PassRegistry &); /// initializeTransformUtils - Initialize all passes linked into the /// TransformUtils library. -void initializeTransformUtils(PassRegistry&); +void initializeTransformUtils(PassRegistry &); /// initializeScalarOpts - Initialize all passes linked into the /// ScalarOpts library. -void initializeScalarOpts(PassRegistry&); +void initializeScalarOpts(PassRegistry &); /// initializeObjCARCOpts - Initialize all passes linked into the ObjCARCOpts /// library. -void initializeObjCARCOpts(PassRegistry&); +void initializeObjCARCOpts(PassRegistry &); /// initializeVectorization - Initialize all passes linked into the /// Vectorize library. -void initializeVectorization(PassRegistry&); +void initializeVectorization(PassRegistry &); /// initializeInstCombine - Initialize all passes linked into the /// InstCombine library. -void initializeInstCombine(PassRegistry&); +void initializeInstCombine(PassRegistry &); /// initializeIPO - Initialize all passes linked into the IPO library. -void initializeIPO(PassRegistry&); +void initializeIPO(PassRegistry &); /// initializeInstrumentation - Initialize all passes linked into the /// Instrumentation library. -void initializeInstrumentation(PassRegistry&); +void initializeInstrumentation(PassRegistry &); /// initializeAnalysis - Initialize all passes linked into the Analysis library. -void initializeAnalysis(PassRegistry&); +void initializeAnalysis(PassRegistry &); /// initializeCodeGen - Initialize all passes linked into the CodeGen library. -void initializeCodeGen(PassRegistry&); +void initializeCodeGen(PassRegistry &); /// Initialize all passes linked into the GlobalISel library. void initializeGlobalISel(PassRegistry &Registry); /// initializeCodeGen - Initialize all passes linked into the CodeGen library. -void initializeTarget(PassRegistry&); +void initializeTarget(PassRegistry &); -void initializeAAEvalLegacyPassPass(PassRegistry&); -void initializeAddDiscriminatorsPass(PassRegistry&); -void initializeADCELegacyPassPass(PassRegistry&); +void initializeAAEvalLegacyPassPass(PassRegistry &); +void initializeAddDiscriminatorsPass(PassRegistry &); +void initializeADCELegacyPassPass(PassRegistry &); void initializeBDCELegacyPassPass(PassRegistry &); -void initializeAliasSetPrinterPass(PassRegistry&); -void initializeAlwaysInlinerPass(PassRegistry&); -void initializeArgPromotionPass(PassRegistry&); -void initializeAtomicExpandPass(PassRegistry&); -void initializeSampleProfileLoaderLegacyPassPass(PassRegistry&); -void initializeAlignmentFromAssumptionsPass(PassRegistry&); -void initializeBarrierNoopPass(PassRegistry&); -void initializeBasicAAWrapperPassPass(PassRegistry&); +void initializeAliasSetPrinterPass(PassRegistry &); +void initializeAlwaysInlinerPass(PassRegistry &); +void initializeArgPromotionPass(PassRegistry &); +void initializeAtomicExpandPass(PassRegistry &); +void initializeSampleProfileLoaderLegacyPassPass(PassRegistry &); +void initializeAlignmentFromAssumptionsPass(PassRegistry &); +void initializeBarrierNoopPass(PassRegistry &); +void initializeBasicAAWrapperPassPass(PassRegistry &); void initializeCallGraphWrapperPassPass(PassRegistry &); -void initializeBlockExtractorPassPass(PassRegistry&); -void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry&); -void initializeBoundsCheckingPass(PassRegistry&); -void initializeBranchFolderPassPass(PassRegistry&); -void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry&); -void initializeBreakCriticalEdgesPass(PassRegistry&); -void initializeCallGraphDOTPrinterPass(PassRegistry&); -void initializeCallGraphPrinterLegacyPassPass(PassRegistry&); -void initializeCallGraphViewerPass(PassRegistry&); -void initializeCFGOnlyPrinterPass(PassRegistry&); -void initializeCFGOnlyViewerPass(PassRegistry&); -void initializeCFGPrinterPass(PassRegistry&); -void initializeCFGSimplifyPassPass(PassRegistry&); -void initializeCFLAAWrapperPassPass(PassRegistry&); -void initializeExternalAAWrapperPassPass(PassRegistry&); -void initializeForwardControlFlowIntegrityPass(PassRegistry&); -void initializeFlattenCFGPassPass(PassRegistry&); -void initializeStructurizeCFGPass(PassRegistry&); -void initializeCFGViewerPass(PassRegistry&); -void initializeConstantHoistingPass(PassRegistry&); -void initializeCodeGenPreparePass(PassRegistry&); +void initializeBlockExtractorPassPass(PassRegistry &); +void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry &); +void initializeBoundsCheckingPass(PassRegistry &); +void initializeBranchFolderPassPass(PassRegistry &); +void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry &); +void initializeBreakCriticalEdgesPass(PassRegistry &); +void initializeCallGraphDOTPrinterPass(PassRegistry &); +void initializeCallGraphPrinterLegacyPassPass(PassRegistry &); +void initializeCallGraphViewerPass(PassRegistry &); +void initializeCFGOnlyPrinterPass(PassRegistry &); +void initializeCFGOnlyViewerPass(PassRegistry &); +void initializeCFGPrinterPass(PassRegistry &); +void initializeCFGSimplifyPassPass(PassRegistry &); +void initializeCFLAAWrapperPassPass(PassRegistry &); +void initializeExternalAAWrapperPassPass(PassRegistry &); +void initializeForwardControlFlowIntegrityPass(PassRegistry &); +void initializeFlattenCFGPassPass(PassRegistry &); +void initializeStructurizeCFGPass(PassRegistry &); +void initializeCFGViewerPass(PassRegistry &); +void initializeConstantHoistingPass(PassRegistry &); +void initializeCodeGenPreparePass(PassRegistry &); void initializeConstantMergeLegacyPassPass(PassRegistry &); -void initializeConstantPropagationPass(PassRegistry&); -void initializeMachineCopyPropagationPass(PassRegistry&); -void initializeCostModelAnalysisPass(PassRegistry&); -void initializeCorrelatedValuePropagationPass(PassRegistry&); -void initializeCrossDSOCFIPass(PassRegistry&); -void initializeDAEPass(PassRegistry&); -void initializeDAHPass(PassRegistry&); -void initializeDCELegacyPassPass(PassRegistry&); -void initializeDSELegacyPassPass(PassRegistry&); -void initializeDeadInstEliminationPass(PassRegistry&); -void initializeDeadMachineInstructionElimPass(PassRegistry&); +void initializeConstantPropagationPass(PassRegistry &); +void initializeMachineCopyPropagationPass(PassRegistry &); +void initializeCostModelAnalysisPass(PassRegistry &); +void initializeCorrelatedValuePropagationPass(PassRegistry &); +void initializeCrossDSOCFIPass(PassRegistry &); +void initializeDAEPass(PassRegistry &); +void initializeDAHPass(PassRegistry &); +void initializeDCELegacyPassPass(PassRegistry &); +void initializeDSELegacyPassPass(PassRegistry &); +void initializeDeadInstEliminationPass(PassRegistry &); +void initializeDeadMachineInstructionElimPass(PassRegistry &); void initializeDelinearizationPass(PassRegistry &); -void initializeDependenceAnalysisPass(PassRegistry&); -void initializeDetectDeadLanesPass(PassRegistry&); -void initializeDependenceAnalysisWrapperPassPass(PassRegistry&); -void initializeDivergenceAnalysisPass(PassRegistry&); -void initializeDomOnlyPrinterPass(PassRegistry&); -void initializeDomOnlyViewerPass(PassRegistry&); -void initializeDomPrinterPass(PassRegistry&); -void initializeDomViewerPass(PassRegistry&); -void initializeDominanceFrontierWrapperPassPass(PassRegistry&); -void initializeDominatorTreeWrapperPassPass(PassRegistry&); -void initializeEarlyIfConverterPass(PassRegistry&); -void initializeEdgeBundlesPass(PassRegistry&); -void initializeExpandPostRAPass(PassRegistry&); +void initializeDependenceAnalysisPass(PassRegistry &); +void initializeDetectDeadLanesPass(PassRegistry &); +void initializeDependenceAnalysisWrapperPassPass(PassRegistry &); +void initializeDivergenceAnalysisPass(PassRegistry &); +void initializeDomOnlyPrinterPass(PassRegistry &); +void initializeDomOnlyViewerPass(PassRegistry &); +void initializeDomPrinterPass(PassRegistry &); +void initializeDomViewerPass(PassRegistry &); +void initializeDominanceFrontierWrapperPassPass(PassRegistry &); +void initializeDominatorTreeWrapperPassPass(PassRegistry &); +void initializeEarlyIfConverterPass(PassRegistry &); +void initializeEdgeBundlesPass(PassRegistry &); +void initializeExpandPostRAPass(PassRegistry &); void initializeAAResultsWrapperPassPass(PassRegistry &); -void initializeGCOVProfilerPass(PassRegistry&); -void initializePGOInstrumentationGenLegacyPassPass(PassRegistry&); -void initializePGOInstrumentationUseLegacyPassPass(PassRegistry&); -void initializePGOIndirectCallPromotionLegacyPassPass(PassRegistry&); +void initializeGCOVProfilerPass(PassRegistry &); +void initializePGOInstrumentationGenLegacyPassPass(PassRegistry &); +void initializePGOInstrumentationUseLegacyPassPass(PassRegistry &); +void initializePGOIndirectCallPromotionLegacyPassPass(PassRegistry &); void initializeInstrProfilingLegacyPassPass(PassRegistry &); -void initializeAddressSanitizerPass(PassRegistry&); -void initializeAddressSanitizerModulePass(PassRegistry&); -void initializeMemorySanitizerPass(PassRegistry&); -void initializeThreadSanitizerPass(PassRegistry&); -void initializeSanitizerCoverageModulePass(PassRegistry&); -void initializeDataFlowSanitizerPass(PassRegistry&); -void initializeEfficiencySanitizerPass(PassRegistry&); -void initializeScalarizerPass(PassRegistry&); +void initializeAddressSanitizerPass(PassRegistry &); +void initializeAddressSanitizerModulePass(PassRegistry &); +void initializeMemorySanitizerPass(PassRegistry &); +void initializeThreadSanitizerPass(PassRegistry &); +void initializeSanitizerCoverageModulePass(PassRegistry &); +void initializeDataFlowSanitizerPass(PassRegistry &); +void initializeEfficiencySanitizerPass(PassRegistry &); +void initializeScalarizerPass(PassRegistry &); void initializeEarlyCSELegacyPassPass(PassRegistry &); void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry &); -void initializeExpandISelPseudosPass(PassRegistry&); -void initializeForceFunctionAttrsLegacyPassPass(PassRegistry&); -void initializeGCMachineCodeAnalysisPass(PassRegistry&); -void initializeGCModuleInfoPass(PassRegistry&); -void initializeGuardWideningLegacyPassPass(PassRegistry&); -void initializeGVNLegacyPassPass(PassRegistry&); -void initializeGlobalDCELegacyPassPass(PassRegistry&); -void initializeGlobalOptLegacyPassPass(PassRegistry&); -void initializeGlobalsAAWrapperPassPass(PassRegistry&); -void initializeIPCPPass(PassRegistry&); +void initializeExpandISelPseudosPass(PassRegistry &); +void initializeForceFunctionAttrsLegacyPassPass(PassRegistry &); +void initializeGCMachineCodeAnalysisPass(PassRegistry &); +void initializeGCModuleInfoPass(PassRegistry &); +void initializeGuardWideningLegacyPassPass(PassRegistry &); +void initializeGVNLegacyPassPass(PassRegistry &); +void initializeGlobalDCELegacyPassPass(PassRegistry &); +void initializeGlobalOptLegacyPassPass(PassRegistry &); +void initializeGlobalsAAWrapperPassPass(PassRegistry &); +void initializeIPCPPass(PassRegistry &); void initializeIPSCCPLegacyPassPass(PassRegistry &); -void initializeIVUsersPass(PassRegistry&); -void initializeIfConverterPass(PassRegistry&); -void initializeInductiveRangeCheckEliminationPass(PassRegistry&); -void initializeIndVarSimplifyLegacyPassPass(PassRegistry&); -void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&); -void initializeInlineCostAnalysisPass(PassRegistry&); -void initializeInstructionCombiningPassPass(PassRegistry&); -void initializeInstCountPass(PassRegistry&); -void initializeInstNamerPass(PassRegistry&); +void initializeIVUsersPass(PassRegistry &); +void initializeIfConverterPass(PassRegistry &); +void initializeInductiveRangeCheckEliminationPass(PassRegistry &); +void initializeIndVarSimplifyLegacyPassPass(PassRegistry &); +void initializeInferFunctionAttrsLegacyPassPass(PassRegistry &); +void initializeInlineCostAnalysisPass(PassRegistry &); +void initializeInstructionCombiningPassPass(PassRegistry &); +void initializeInstCountPass(PassRegistry &); +void initializeInstNamerPass(PassRegistry &); void initializeInterleavedAccessPass(PassRegistry &); -void initializeInternalizeLegacyPassPass(PassRegistry&); -void initializeIntervalPartitionPass(PassRegistry&); +void initializeInternalizeLegacyPassPass(PassRegistry &); +void initializeIntervalPartitionPass(PassRegistry &); void initializeIRTranslatorPass(PassRegistry &); -void initializeJumpThreadingPass(PassRegistry&); -void initializeLCSSAPass(PassRegistry&); -void initializeLICMPass(PassRegistry&); -void initializeLazyValueInfoPass(PassRegistry&); -void initializeLintPass(PassRegistry&); -void initializeLiveDebugVariablesPass(PassRegistry&); -void initializeLiveIntervalsPass(PassRegistry&); -void initializeLiveRegMatrixPass(PassRegistry&); -void initializeLiveStacksPass(PassRegistry&); -void initializeLiveVariablesPass(PassRegistry&); -void initializeLoaderPassPass(PassRegistry&); -void initializeLocalStackSlotPassPass(PassRegistry&); -void initializeLoopDataPrefetchPass(PassRegistry&); -void initializeLoopPassPass(PassRegistry&); -void initializeLoopDeletionPass(PassRegistry&); -void initializeLoopExtractorPass(PassRegistry&); -void initializeLoopInfoWrapperPassPass(PassRegistry&); +void initializeJumpThreadingPass(PassRegistry &); +void initializeLCSSAPass(PassRegistry &); +void initializeLICMPass(PassRegistry &); +void initializeLazyValueInfoPass(PassRegistry &); +void initializeLintPass(PassRegistry &); +void initializeLiveDebugVariablesPass(PassRegistry &); +void initializeLiveIntervalsPass(PassRegistry &); +void initializeLiveRegMatrixPass(PassRegistry &); +void initializeLiveStacksPass(PassRegistry &); +void initializeLiveVariablesPass(PassRegistry &); +void initializeLoaderPassPass(PassRegistry &); +void initializeLocalStackSlotPassPass(PassRegistry &); +void initializeLoopDataPrefetchPass(PassRegistry &); +void initializeLoopPassPass(PassRegistry &); +void initializeLoopDeletionPass(PassRegistry &); +void initializeLoopExtractorPass(PassRegistry &); +void initializeLoopInfoWrapperPassPass(PassRegistry &); void initializeLoopInterchangePass(PassRegistry &); -void initializeLoopInstSimplifyPass(PassRegistry&); -void initializeLoopRotateLegacyPassPass(PassRegistry&); -void initializeLoopSimplifyPass(PassRegistry&); -void initializeLoopSimplifyCFGLegacyPassPass(PassRegistry&); -void initializeLoopStrengthReducePass(PassRegistry&); -void initializeGlobalMergePass(PassRegistry&); -void initializeLoopRerollPass(PassRegistry&); -void initializeLoopUnrollPass(PassRegistry&); -void initializeLoopUnswitchPass(PassRegistry&); -void initializeLoopVersioningLICMPass(PassRegistry&); -void initializeLoopIdiomRecognizePass(PassRegistry&); +void initializeLoopInstSimplifyPass(PassRegistry &); +void initializeLoopRotateLegacyPassPass(PassRegistry &); +void initializeLoopSimplifyPass(PassRegistry &); +void initializeLoopSimplifyCFGLegacyPassPass(PassRegistry &); +void initializeLoopStrengthReducePass(PassRegistry &); +void initializeGlobalMergePass(PassRegistry &); +void initializeLoopRerollPass(PassRegistry &); +void initializeLoopUnrollPass(PassRegistry &); +void initializeLoopUnswitchPass(PassRegistry &); +void initializeLoopVersioningLICMPass(PassRegistry &); +void initializeLoopIdiomRecognizePass(PassRegistry &); void initializeLowerAtomicLegacyPassPass(PassRegistry &); -void initializeLowerBitSetsPass(PassRegistry&); -void initializeLowerExpectIntrinsicPass(PassRegistry&); -void initializeLowerGuardIntrinsicPass(PassRegistry&); -void initializeLowerIntrinsicsPass(PassRegistry&); -void initializeLowerInvokePass(PassRegistry&); -void initializeLowerSwitchPass(PassRegistry&); -void initializeLowerEmuTLSPass(PassRegistry&); -void initializeMachineBlockFrequencyInfoPass(PassRegistry&); -void initializeMachineBlockPlacementPass(PassRegistry&); -void initializeMachineBlockPlacementStatsPass(PassRegistry&); -void initializeMachineBranchProbabilityInfoPass(PassRegistry&); -void initializeMachineCSEPass(PassRegistry&); +void initializeLowerBitSetsPass(PassRegistry &); +void initializeLowerExpectIntrinsicPass(PassRegistry &); +void initializeLowerGuardIntrinsicPass(PassRegistry &); +void initializeLowerIntrinsicsPass(PassRegistry &); +void initializeLowerInvokePass(PassRegistry &); +void initializeLowerSwitchPass(PassRegistry &); +void initializeLowerEmuTLSPass(PassRegistry &); +void initializeMachineBlockFrequencyInfoPass(PassRegistry &); +void initializeMachineBlockPlacementPass(PassRegistry &); +void initializeMachineBlockPlacementStatsPass(PassRegistry &); +void initializeMachineBranchProbabilityInfoPass(PassRegistry &); +void initializeMachineCSEPass(PassRegistry &); void initializeModuleSummaryIndexWrapperPassPass(PassRegistry &); -void initializeImplicitNullChecksPass(PassRegistry&); -void initializeMachineDominatorTreePass(PassRegistry&); -void initializeMachineDominanceFrontierPass(PassRegistry&); -void initializeMachinePostDominatorTreePass(PassRegistry&); -void initializeMachineLICMPass(PassRegistry&); -void initializeMachineLoopInfoPass(PassRegistry&); -void initializeMachineModuleInfoPass(PassRegistry&); -void initializeMachineRegionInfoPassPass(PassRegistry&); -void initializeMachineSchedulerPass(PassRegistry&); -void initializeMachineSinkingPass(PassRegistry&); -void initializeMachineTraceMetricsPass(PassRegistry&); -void initializeMachineVerifierPassPass(PassRegistry&); -void initializeMemCpyOptPass(PassRegistry&); -void initializeMemDepPrinterPass(PassRegistry&); -void initializeMemDerefPrinterPass(PassRegistry&); -void initializeMemoryDependenceWrapperPassPass(PassRegistry&); -void initializeMemorySSALazyPass(PassRegistry&); -void initializeMemorySSAPrinterPassPass(PassRegistry&); +void initializeImplicitNullChecksPass(PassRegistry &); +void initializeMachineDominatorTreePass(PassRegistry &); +void initializeMachineDominanceFrontierPass(PassRegistry &); +void initializeMachinePostDominatorTreePass(PassRegistry &); +void initializeMachineLICMPass(PassRegistry &); +void initializeMachineLoopInfoPass(PassRegistry &); +void initializeMachineModuleInfoPass(PassRegistry &); +void initializeMachineRegionInfoPassPass(PassRegistry &); +void initializeMachineSchedulerPass(PassRegistry &); +void initializeMachineSinkingPass(PassRegistry &); +void initializeMachineTraceMetricsPass(PassRegistry &); +void initializeMachineVerifierPassPass(PassRegistry &); +void initializeMemCpyOptPass(PassRegistry &); +void initializeMemDepPrinterPass(PassRegistry &); +void initializeMemDerefPrinterPass(PassRegistry &); +void initializeMemoryDependenceWrapperPassPass(PassRegistry &); +void initializeMemorySSALazyPass(PassRegistry &); +void initializeMemorySSAPrinterPassPass(PassRegistry &); void initializeMergedLoadStoreMotionPass(PassRegistry &); -void initializeMetaRenamerPass(PassRegistry&); -void initializeMergeFunctionsPass(PassRegistry&); -void initializeModuleDebugInfoPrinterPass(PassRegistry&); +void initializeMetaRenamerPass(PassRegistry &); +void initializeMergeFunctionsPass(PassRegistry &); +void initializeModuleDebugInfoPrinterPass(PassRegistry &); void initializeNameAnonFunctionPass(PassRegistry &); -void initializeNaryReassociatePass(PassRegistry&); -void initializeNoAAPass(PassRegistry&); -void initializeObjCARCAAWrapperPassPass(PassRegistry&); -void initializeObjCARCAPElimPass(PassRegistry&); -void initializeObjCARCExpandPass(PassRegistry&); -void initializeObjCARCContractPass(PassRegistry&); -void initializeObjCARCOptPass(PassRegistry&); +void initializeNaryReassociatePass(PassRegistry &); +void initializeNoAAPass(PassRegistry &); +void initializeObjCARCAAWrapperPassPass(PassRegistry &); +void initializeObjCARCAPElimPass(PassRegistry &); +void initializeObjCARCExpandPass(PassRegistry &); +void initializeObjCARCContractPass(PassRegistry &); +void initializeObjCARCOptPass(PassRegistry &); void initializePAEvalPass(PassRegistry &); -void initializeOptimizePHIsPass(PassRegistry&); +void initializeOptimizePHIsPass(PassRegistry &); void initializePartiallyInlineLibCallsLegacyPassPass(PassRegistry &); -void initializePEIPass(PassRegistry&); -void initializePHIEliminationPass(PassRegistry&); -void initializePartialInlinerPass(PassRegistry&); -void initializePeepholeOptimizerPass(PassRegistry&); -void initializePostDomOnlyPrinterPass(PassRegistry&); -void initializePostDomOnlyViewerPass(PassRegistry&); -void initializePostDomPrinterPass(PassRegistry&); -void initializePostDomViewerPass(PassRegistry&); -void initializePostDominatorTreeWrapperPassPass(PassRegistry&); -void initializePostOrderFunctionAttrsLegacyPassPass(PassRegistry&); -void initializePostRAHazardRecognizerPass(PassRegistry&); -void initializePostRASchedulerPass(PassRegistry&); -void initializePostMachineSchedulerPass(PassRegistry&); -void initializePreISelIntrinsicLoweringPass(PassRegistry&); -void initializePrintFunctionPassWrapperPass(PassRegistry&); -void initializePrintModulePassWrapperPass(PassRegistry&); -void initializePrintBasicBlockPassPass(PassRegistry&); -void initializeProcessImplicitDefsPass(PassRegistry&); -void initializePromotePassPass(PassRegistry&); -void initializePruneEHPass(PassRegistry&); -void initializeReassociateLegacyPassPass(PassRegistry&); +void initializePEIPass(PassRegistry &); +void initializePHIEliminationPass(PassRegistry &); +void initializePhysicalRegisterUsageInfoPass(PassRegistry &); +void initializePartialInlinerPass(PassRegistry &); +void initializePeepholeOptimizerPass(PassRegistry &); +void initializePostDomOnlyPrinterPass(PassRegistry &); +void initializePostDomOnlyViewerPass(PassRegistry &); +void initializePostDomPrinterPass(PassRegistry &); +void initializePostDomViewerPass(PassRegistry &); +void initializePostDominatorTreeWrapperPassPass(PassRegistry &); +void initializePostOrderFunctionAttrsLegacyPassPass(PassRegistry &); +void initializePostRAHazardRecognizerPass(PassRegistry &); +void initializePostRASchedulerPass(PassRegistry &); +void initializePostMachineSchedulerPass(PassRegistry &); +void initializePreISelIntrinsicLoweringPass(PassRegistry &); +void initializePrintFunctionPassWrapperPass(PassRegistry &); +void initializePrintModulePassWrapperPass(PassRegistry &); +void initializePrintBasicBlockPassPass(PassRegistry &); +void initializeProcessImplicitDefsPass(PassRegistry &); +void initializePromotePassPass(PassRegistry &); +void initializePruneEHPass(PassRegistry &); +void initializeReassociateLegacyPassPass(PassRegistry &); void initializeRegBankSelectPass(PassRegistry &); -void initializeRegToMemPass(PassRegistry&); -void initializeRegionInfoPassPass(PassRegistry&); -void initializeRegionOnlyPrinterPass(PassRegistry&); -void initializeRegionOnlyViewerPass(PassRegistry&); -void initializeRegionPrinterPass(PassRegistry&); -void initializeRegionViewerPass(PassRegistry&); -void initializeReversePostOrderFunctionAttrsPass(PassRegistry&); -void initializeRewriteStatepointsForGCPass(PassRegistry&); -void initializeSafeStackPass(PassRegistry&); +void initializeRegToMemPass(PassRegistry &); +void initializeRegionInfoPassPass(PassRegistry &); +void initializeRegionOnlyPrinterPass(PassRegistry &); +void initializeRegionOnlyViewerPass(PassRegistry &); +void initializeRegionPrinterPass(PassRegistry &); +void initializeRegionViewerPass(PassRegistry &); +void initializeReversePostOrderFunctionAttrsPass(PassRegistry &); +void initializeRewriteStatepointsForGCPass(PassRegistry &); +void initializeSafeStackPass(PassRegistry &); void initializeSCCPLegacyPassPass(PassRegistry &); -void initializeSROALegacyPassPass(PassRegistry&); -void initializeSROA_DTPass(PassRegistry&); -void initializeSROA_SSAUpPass(PassRegistry&); -void initializeSCEVAAWrapperPassPass(PassRegistry&); -void initializeScalarEvolutionWrapperPassPass(PassRegistry&); +void initializeSROALegacyPassPass(PassRegistry &); +void initializeSROA_DTPass(PassRegistry &); +void initializeSROA_SSAUpPass(PassRegistry &); +void initializeSCEVAAWrapperPassPass(PassRegistry &); +void initializeScalarEvolutionWrapperPassPass(PassRegistry &); void initializeShrinkWrapPass(PassRegistry &); -void initializeSimpleInlinerPass(PassRegistry&); -void initializeShadowStackGCLoweringPass(PassRegistry&); -void initializeRegisterCoalescerPass(PassRegistry&); -void initializeSingleLoopExtractorPass(PassRegistry&); -void initializeSinkingLegacyPassPass(PassRegistry&); +void initializeSimpleInlinerPass(PassRegistry &); +void initializeShadowStackGCLoweringPass(PassRegistry &); +void initializeRegisterCoalescerPass(PassRegistry &); +void initializeSingleLoopExtractorPass(PassRegistry &); +void initializeSinkingLegacyPassPass(PassRegistry &); void initializeSeparateConstOffsetFromGEPPass(PassRegistry &); -void initializeSlotIndexesPass(PassRegistry&); -void initializeSpillPlacementPass(PassRegistry&); -void initializeSpeculativeExecutionPass(PassRegistry&); -void initializeStackProtectorPass(PassRegistry&); -void initializeStackColoringPass(PassRegistry&); -void initializeStackSlotColoringPass(PassRegistry&); +void initializeSlotIndexesPass(PassRegistry &); +void initializeSpillPlacementPass(PassRegistry &); +void initializeSpeculativeExecutionPass(PassRegistry &); +void initializeStackProtectorPass(PassRegistry &); +void initializeStackColoringPass(PassRegistry &); +void initializeStackSlotColoringPass(PassRegistry &); void initializeStraightLineStrengthReducePass(PassRegistry &); -void initializeStripDeadDebugInfoPass(PassRegistry&); -void initializeStripDeadPrototypesLegacyPassPass(PassRegistry&); -void initializeStripDebugDeclarePass(PassRegistry&); -void initializeStripNonDebugSymbolsPass(PassRegistry&); -void initializeStripSymbolsPass(PassRegistry&); -void initializeTailCallElimPass(PassRegistry&); -void initializeTailDuplicatePassPass(PassRegistry&); -void initializeTargetPassConfigPass(PassRegistry&); +void initializeStripDeadDebugInfoPass(PassRegistry &); +void initializeStripDeadPrototypesLegacyPassPass(PassRegistry &); +void initializeStripDebugDeclarePass(PassRegistry &); +void initializeStripNonDebugSymbolsPass(PassRegistry &); +void initializeStripSymbolsPass(PassRegistry &); +void initializeTailCallElimPass(PassRegistry &); +void initializeTailDuplicatePassPass(PassRegistry &); +void initializeTargetPassConfigPass(PassRegistry &); void initializeTargetTransformInfoWrapperPassPass(PassRegistry &); void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &); void initializeAssumptionCacheTrackerPass(PassRegistry &); -void initializeTwoAddressInstructionPassPass(PassRegistry&); -void initializeTypeBasedAAWrapperPassPass(PassRegistry&); -void initializeScopedNoAliasAAWrapperPassPass(PassRegistry&); -void initializeUnifyFunctionExitNodesPass(PassRegistry&); -void initializeUnreachableBlockElimPass(PassRegistry&); -void initializeUnreachableMachineBlockElimPass(PassRegistry&); -void initializeVerifierLegacyPassPass(PassRegistry&); -void initializeVirtRegMapPass(PassRegistry&); -void initializeVirtRegRewriterPass(PassRegistry&); -void initializeInstSimplifierPass(PassRegistry&); -void initializeUnpackMachineBundlesPass(PassRegistry&); -void initializeFinalizeMachineBundlesPass(PassRegistry&); -void initializeLoopAccessAnalysisPass(PassRegistry&); -void initializeLoopVectorizePass(PassRegistry&); -void initializeSLPVectorizerPass(PassRegistry&); -void initializeBBVectorizePass(PassRegistry&); -void initializeMachineFunctionPrinterPassPass(PassRegistry&); -void initializeMIRPrintingPassPass(PassRegistry&); -void initializeStackMapLivenessPass(PassRegistry&); -void initializeLiveDebugValuesPass(PassRegistry&); +void initializeTwoAddressInstructionPassPass(PassRegistry &); +void initializeTypeBasedAAWrapperPassPass(PassRegistry &); +void initializeScopedNoAliasAAWrapperPassPass(PassRegistry &); +void initializeUnifyFunctionExitNodesPass(PassRegistry &); +void initializeUnreachableBlockElimPass(PassRegistry &); +void initializeUnreachableMachineBlockElimPass(PassRegistry &); +void initializeVerifierLegacyPassPass(PassRegistry &); +void initializeVirtRegMapPass(PassRegistry &); +void initializeVirtRegRewriterPass(PassRegistry &); +void initializeInstSimplifierPass(PassRegistry &); +void initializeUnpackMachineBundlesPass(PassRegistry &); +void initializeFinalizeMachineBundlesPass(PassRegistry &); +void initializeLoopAccessAnalysisPass(PassRegistry &); +void initializeLoopVectorizePass(PassRegistry &); +void initializeSLPVectorizerPass(PassRegistry &); +void initializeBBVectorizePass(PassRegistry &); +void initializeMachineFunctionPrinterPassPass(PassRegistry &); +void initializeMIRPrintingPassPass(PassRegistry &); +void initializeStackMapLivenessPass(PassRegistry &); +void initializeLiveDebugValuesPass(PassRegistry &); void initializeMachineCombinerPass(PassRegistry &); -void initializeLoadCombinePass(PassRegistry&); -void initializeRewriteSymbolsPass(PassRegistry&); -void initializeWinEHPreparePass(PassRegistry&); +void initializeLoadCombinePass(PassRegistry &); +void initializeRewriteSymbolsPass(PassRegistry &); +void initializeWinEHPreparePass(PassRegistry &); void initializeWriteBitcodePassPass(PassRegistry &); -void initializePlaceBackedgeSafepointsImplPass(PassRegistry&); -void initializePlaceSafepointsPass(PassRegistry&); -void initializeDwarfEHPreparePass(PassRegistry&); -void initializeFloat2IntPass(PassRegistry&); -void initializeLoopDistributePass(PassRegistry&); -void initializeSjLjEHPreparePass(PassRegistry&); -void initializeDemandedBitsWrapperPassPass(PassRegistry&); +void initializePlaceBackedgeSafepointsImplPass(PassRegistry &); +void initializePlaceSafepointsPass(PassRegistry &); +void initializeDwarfEHPreparePass(PassRegistry &); +void initializeFloat2IntPass(PassRegistry &); +void initializeLoopDistributePass(PassRegistry &); +void initializeSjLjEHPreparePass(PassRegistry &); +void initializeDemandedBitsWrapperPassPass(PassRegistry &); void initializeFuncletLayoutPass(PassRegistry &); -void initializeLoopLoadEliminationPass(PassRegistry&); +void initializeLoopLoadEliminationPass(PassRegistry &); void initializeFunctionImportPassPass(PassRegistry &); void initializeLoopVersioningPassPass(PassRegistry &); void initializeWholeProgramDevirtPass(PassRegistry &); Index: lib/CodeGen/CMakeLists.txt =================================================================== --- lib/CodeGen/CMakeLists.txt +++ lib/CodeGen/CMakeLists.txt @@ -85,6 +85,7 @@ PeepholeOptimizer.cpp PHIElimination.cpp PHIEliminationUtils.cpp + PhysicalRegisterUsageInfo.cpp PostRAHazardRecognizer.cpp PostRASchedulerList.cpp PreISelIntrinsicLowering.cpp @@ -100,6 +101,7 @@ RegisterCoalescer.cpp RegisterPressure.cpp RegisterScavenging.cpp + RegUsageInfoCollector.cpp SafeStack.cpp ScheduleDAG.cpp ScheduleDAGInstrs.cpp Index: lib/CodeGen/PhysicalRegisterUsageInfo.cpp =================================================================== --- /dev/null +++ lib/CodeGen/PhysicalRegisterUsageInfo.cpp @@ -0,0 +1,47 @@ +//=- PhysicalRegisterUsageInfo.cpp - Register Usage Informartion Storage -*- C++ +//-*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass is required to get Interprocedural Register Allocation effect. +// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and +// lib/CodeGen/RegUsageInfoCollector.cpp +// +// This pass is simple immutable pass which keeps StringMap of +// function name to RegMask (calculated based on actual register allocation) and +// provides simple API to query this information. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "ipra" + +INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info", + "Register Usage Informartion Stroage", false, true) + +char PhysicalRegisterUsageInfo::ID = 0; + +void PhysicalRegisterUsageInfo::anchor() {} + +void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo( + StringRef MFName, std::vector RegMask) { + RegMasks[MFName] = std::move(RegMask); +} + +const std::vector * +PhysicalRegisterUsageInfo::getRegUsageInfo(StringRef MFName) { + if (RegMasks.find(MFName) != RegMasks.end()) + return &(RegMasks.find(MFName)->second); + else + return nullptr; +} Index: lib/CodeGen/RegUsageInfoCollector.cpp =================================================================== --- /dev/null +++ lib/CodeGen/RegUsageInfoCollector.cpp @@ -0,0 +1,114 @@ +//=- RegUsageInfoCollector.cpp - Register Usage Informartion Collector -*- C++ +//-*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass is required to get Interprocedural Register Allocation effect. +// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and +// lib/CodeGen/PhysicalRegisterUsageInfo.cpp +// +// This pass is simple MachineFunction pass which collects register usage +// details by iterating through +// each physical registers and checking MRI::isPhysRegUsed() then creates a +// RegMask based on this details. +// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "ipra" + +namespace llvm { +void initializeRegUsageInfoCollectorPass(PassRegistry &); +} + +namespace { +class RegUsageInfoCollector : public MachineFunctionPass { +public: + RegUsageInfoCollector() : MachineFunctionPass(ID) {} + + const char *getPassName() const override { + return "Register Usage Information Collector Pass"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override; + + bool runOnMachineFunction(MachineFunction &MF) override; + + static char ID; +}; +} + +char RegUsageInfoCollector::ID = 0; + +INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", + "Register Usage Information Collector Pass", false, false) +INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo) +INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector", + "Register Usage Information Collector Pass", false, false) + +FunctionPass *llvm::createRegUsageInfoCollector() { + return new RegUsageInfoCollector(); +} + +void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { + bool changed = false; + MachineRegisterInfo *MRI = &MF.getRegInfo(); + TargetRegisterInfo *TRI = + (TargetRegisterInfo *)MF.getSubtarget().getRegisterInfo(); + + DEBUG(dbgs() << " -------------------- Register Usage Collection Pass " + "----------------------- \n"); + DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n"); + + std::vector RegMask; + unsigned regMaskSize = + (TRI->getNumRegs() + 31) / 32; // size should be in multiple of 32. + RegMask.resize(regMaskSize, 0); + + PhysicalRegisterUsageInfo *PRUI = &getAnalysis(); + + for (unsigned PReg = 1; PReg < TRI->getNumRegs(); ++PReg) { + if (!MRI->reg_nodbg_empty(PReg)) { + if (MRI->isPhysRegUsed(PReg)) { + // If PReg is clobbered then all of its alias are also clobbered + for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) { + RegMask[*AI / 32] |= 1u << *AI % 32; + } + } + } + } + + DEBUG(dbgs() << " -----------------------------------------------------------" + "------------------ \n"); + + // bitwise negation for RegMask because 0 means clobbred and 1 means preserved + for (unsigned index = 0; index < regMaskSize; index++) { + RegMask[index] = ~RegMask[index]; + } + + PRUI->storeUpdateRegUsageInfo(MF.getName(), std::move(RegMask)); + + return changed; +} Index: lib/CodeGen/TargetPassConfig.cpp =================================================================== --- lib/CodeGen/TargetPassConfig.cpp +++ lib/CodeGen/TargetPassConfig.cpp @@ -20,6 +20,7 @@ #include "llvm/Analysis/ScopedNoAliasAA.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/LegacyPassManager.h" @@ -37,80 +38,102 @@ using namespace llvm; static cl::opt DisablePostRA("disable-post-ra", cl::Hidden, - cl::desc("Disable Post Regalloc")); + cl::desc("Disable Post Regalloc")); static cl::opt DisableBranchFold("disable-branch-fold", cl::Hidden, - cl::desc("Disable branch folding")); + cl::desc("Disable branch folding")); static cl::opt DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, - cl::desc("Disable tail duplication")); -static cl::opt DisableEarlyTailDup("disable-early-taildup", cl::Hidden, + cl::desc("Disable tail duplication")); +static cl::opt DisableEarlyTailDup( + "disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication")); -static cl::opt DisableBlockPlacement("disable-block-placement", - cl::Hidden, cl::desc("Disable probability-driven block placement")); -static cl::opt EnableBlockPlacementStats("enable-block-placement-stats", - cl::Hidden, cl::desc("Collect probability-driven block placement stats")); +static cl::opt DisableBlockPlacement( + "disable-block-placement", cl::Hidden, + cl::desc("Disable probability-driven block placement")); +static cl::opt EnableBlockPlacementStats( + "enable-block-placement-stats", cl::Hidden, + cl::desc("Collect probability-driven block placement stats")); static cl::opt DisableSSC("disable-ssc", cl::Hidden, - cl::desc("Disable Stack Slot Coloring")); -static cl::opt DisableMachineDCE("disable-machine-dce", cl::Hidden, - cl::desc("Disable Machine Dead Code Elimination")); -static cl::opt DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, - cl::desc("Disable Early If-conversion")); + cl::desc("Disable Stack Slot Coloring")); +static cl::opt + DisableMachineDCE("disable-machine-dce", cl::Hidden, + cl::desc("Disable Machine Dead Code Elimination")); +static cl::opt + DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, + cl::desc("Disable Early If-conversion")); static cl::opt DisableMachineLICM("disable-machine-licm", cl::Hidden, - cl::desc("Disable Machine LICM")); -static cl::opt DisableMachineCSE("disable-machine-cse", cl::Hidden, + cl::desc("Disable Machine LICM")); +static cl::opt DisableMachineCSE( + "disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination")); static cl::opt OptimizeRegAlloc( "optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path.")); static cl::opt DisablePostRAMachineLICM("disable-postra-machine-licm", - cl::Hidden, - cl::desc("Disable Machine LICM")); + cl::Hidden, + cl::desc("Disable Machine LICM")); static cl::opt DisableMachineSink("disable-machine-sink", cl::Hidden, - cl::desc("Disable Machine Sinking")); -static cl::opt DisableLSR("disable-lsr", cl::Hidden, - cl::desc("Disable Loop Strength Reduction Pass")); -static cl::opt DisableConstantHoisting("disable-constant-hoisting", - cl::Hidden, cl::desc("Disable ConstantHoisting")); + cl::desc("Disable Machine Sinking")); +static cl::opt + DisableLSR("disable-lsr", cl::Hidden, + cl::desc("Disable Loop Strength Reduction Pass")); +static cl::opt + DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, + cl::desc("Disable ConstantHoisting")); static cl::opt DisableCGP("disable-cgp", cl::Hidden, - cl::desc("Disable Codegen Prepare")); + cl::desc("Disable Codegen Prepare")); static cl::opt DisableCopyProp("disable-copyprop", cl::Hidden, - cl::desc("Disable Copy Propagation pass")); -static cl::opt DisablePartialLibcallInlining("disable-partial-libcall-inlining", - cl::Hidden, cl::desc("Disable Partial Libcall Inlining")); + cl::desc("Disable Copy Propagation pass")); +static cl::opt + DisablePartialLibcallInlining("disable-partial-libcall-inlining", + cl::Hidden, + cl::desc("Disable Partial Libcall Inlining")); static cl::opt EnableImplicitNullChecks( "enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false)); -static cl::opt PrintLSR("print-lsr-output", cl::Hidden, - cl::desc("Print LLVM IR produced by the loop-reduce pass")); -static cl::opt PrintISelInput("print-isel-input", cl::Hidden, - cl::desc("Print LLVM IR input to isel pass")); +static cl::opt + PrintLSR("print-lsr-output", cl::Hidden, + cl::desc("Print LLVM IR produced by the loop-reduce pass")); +static cl::opt + PrintISelInput("print-isel-input", cl::Hidden, + cl::desc("Print LLVM IR input to isel pass")); static cl::opt PrintGCInfo("print-gc", cl::Hidden, - cl::desc("Dump garbage collector data")); -static cl::opt VerifyMachineCode("verify-machineinstrs", cl::Hidden, - cl::desc("Verify generated machine code"), - cl::init(false), - cl::ZeroOrMore); - -static cl::opt -PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, - cl::desc("Print machine instrs"), - cl::value_desc("pass-name"), cl::init("option-unspecified")); + cl::desc("Dump garbage collector data")); +static cl::opt + VerifyMachineCode("verify-machineinstrs", cl::Hidden, + cl::desc("Verify generated machine code"), + cl::init(false), cl::ZeroOrMore); + +static cl::opt PrintMachineInstrs("print-machineinstrs", + cl::ValueOptional, + cl::desc("Print machine instrs"), + cl::value_desc("pass-name"), + cl::init("option-unspecified")); // Temporary option to allow experimenting with MachineScheduler as a post-RA // scheduler. Targets can "properly" enable this with // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID). // Targets can return true in targetSchedulesPostRAScheduling() and // insert a PostRA scheduling pass wherever it wants. -cl::opt MISchedPostRA("misched-postra", cl::Hidden, - cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")); +cl::opt MISchedPostRA( + "misched-postra", cl::Hidden, + cl::desc( + "Run MachineScheduler post regalloc (independent of preRA sched)")); // Experimental option to run live interval analysis early. -static cl::opt EarlyLiveIntervals("early-live-intervals", cl::Hidden, +static cl::opt EarlyLiveIntervals( + "early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline")); -static cl::opt UseCFLAA("use-cfl-aa-in-codegen", - cl::init(false), cl::Hidden, - cl::desc("Enable the new, experimental CFL alias analysis in CodeGen")); +static cl::opt UseCFLAA( + "use-cfl-aa-in-codegen", cl::init(false), cl::Hidden, + cl::desc("Enable the new, experimental CFL alias analysis in CodeGen")); + +// Option to enable compile time interprocedural register allocation. +cl::opt + UseIPRA("enable-ipra", cl::init(false), + cl::desc("Enable compile time interprocedural register allocation " + "to reduce load/store at procedure calls.")); /// Allow standard passes to be disabled by command line options. This supports /// simple binary flags that either suppress the pass or do nothing. @@ -224,7 +247,7 @@ // user interface. For example, a target may disable a standard pass by // default by substituting a pass ID of zero, and the user may still enable // that standard pass with an explicit command line option. - DenseMap TargetPasses; + DenseMap TargetPasses; /// Store the pairs of of which the second pass /// is inserted after each instance of the first one. @@ -233,9 +256,7 @@ } // namespace llvm // Out of line virtual method. -TargetPassConfig::~TargetPassConfig() { - delete Impl; -} +TargetPassConfig::~TargetPassConfig() { delete Impl; } // Out of line constructor provides default values for pass options and // registers all common codegen passes. @@ -288,8 +309,7 @@ return new TargetPassConfig(this, PM); } -TargetPassConfig::TargetPassConfig() - : ImmutablePass(ID), PM(nullptr) { +TargetPassConfig::TargetPassConfig() : ImmutablePass(ID), PM(nullptr) { llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); } @@ -305,8 +325,8 @@ } IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { - DenseMap::const_iterator - I = Impl->TargetPasses.find(ID); + DenseMap::const_iterator I = + Impl->TargetPasses.find(ID); if (I == Impl->TargetPasses.end()) return ID; return I->second; @@ -315,8 +335,7 @@ bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const { IdentifyingPassPtr TargetID = getPassSubstitution(ID); IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID); - return !FinalPtr.isValid() || FinalPtr.isInstance() || - FinalPtr.getID() != ID; + return !FinalPtr.isValid() || FinalPtr.isInstance() || FinalPtr.getID() != ID; } /// Add a pass to the PassManager if that pass is supposed to be run. If the @@ -458,7 +477,7 @@ // pad is shared by multiple invokes and is also a target of a normal // edge from elsewhere. addPass(createSjLjEHPreparePass()); - // FALLTHROUGH + // FALLTHROUGH case ExceptionHandling::DwarfCFI: case ExceptionHandling::ARM: addPass(createDwarfEHPass(TM)); @@ -487,11 +506,41 @@ addPass(createRewriteSymbolsPass()); } +#include "llvm/Analysis/CallGraphSCCPass.h" +namespace llvm { +void initializeDummyCGSCCPassPass(PassRegistry &); +} +namespace { +class DummyCGSCCPass : public CallGraphSCCPass { +public: + static char ID; + DummyCGSCCPass() : CallGraphSCCPass(ID){}; + bool runOnSCC(CallGraphSCC &SCC) override { return false; } + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesAll(); + } +}; +} + +char DummyCGSCCPass::ID = 0; +INITIALIZE_PASS_BEGIN(DummyCGSCCPass, "DummyCGSCCPass", "DummyCGSCCPass", false, + false) +INITIALIZE_PASS_DEPENDENCY(CallGraphWrapperPass) +INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) +INITIALIZE_PASS_END(DummyCGSCCPass, "DummyCGSCCPass", "DummyCGSCCPass", false, + false) + /// Add common passes that perform LLVM IR to IR transforms in preparation for /// instruction selection. void TargetPassConfig::addISelPrepare() { addPreISel(); + if (UseIPRA) { + // FORCE CODEGEN TO RUN ACCORDING TO THE CALLGRAPH + initializeDummyCGSCCPassPass(*PassRegistry::getPassRegistry()); + addPass(new DummyCGSCCPass); + } + // Add both the safe stack and the stack protection passes: each of them will // only protect functions that have corresponding attributes. addPass(createSafeStackPass(TM)); @@ -534,7 +583,7 @@ const PassRegistry *PR = PassRegistry::getPassRegistry(); const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); - assert (TPI && IPI && "Pass ID not registered!"); + assert(TPI && IPI && "Pass ID not registered!"); const char *TID = (const char *)(TPI->getTypeInfo()); const char *IID = (const char *)(IPI->getTypeInfo()); insertPass(TID, IID); @@ -568,6 +617,12 @@ // Run post-ra passes. addPostRegAlloc(); + if (UseIPRA) { + // this is MachineFunction pass which iterates through register + // to check if it is used or not and creates RegMask + addPass(createRegUsageInfoCollector()); + } + // Insert prolog/epilog code. Eliminate abstract frame index references... if (getOptLevel() != CodeGenOpt::None) addPass(&ShrinkWrapID); @@ -575,7 +630,7 @@ // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only // do so if it hasn't been disabled, substituted, or overridden. if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID)) - addPass(createPrologEpilogInserterPass(TM)); + addPass(createPrologEpilogInserterPass(TM)); /// Add passes that optimize machine instructions after register allocation. if (getOptLevel() != CodeGenOpt::None) @@ -667,9 +722,12 @@ bool TargetPassConfig::getOptimizeRegAlloc() const { switch (OptimizeRegAlloc) { - case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; - case cl::BOU_TRUE: return true; - case cl::BOU_FALSE: return false; + case cl::BOU_UNSET: + return getOptLevel() != CodeGenOpt::None; + case cl::BOU_TRUE: + return true; + case cl::BOU_FALSE: + return false; } llvm_unreachable("Invalid optimize-regalloc state"); } @@ -681,17 +739,14 @@ /// overridden on the command line. static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } static RegisterRegAlloc -defaultRegAlloc("default", - "pick register allocator based on -O option", - useDefaultRegisterAllocator); + defaultRegAlloc("default", "pick register allocator based on -O option", + useDefaultRegisterAllocator); /// -regalloc=... command line option. static cl::opt > -RegAlloc("regalloc", - cl::init(&useDefaultRegisterAllocator), - cl::desc("Register allocator to use")); - + RegisterPassParser> + RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator), + cl::desc("Register allocator to use")); /// Instantiate the default register allocator pass for this target for either /// the optimized or unoptimized allocation path. This will be added to the pass Index: lib/Target/X86/CMakeLists.txt =================================================================== --- lib/Target/X86/CMakeLists.txt +++ lib/Target/X86/CMakeLists.txt @@ -26,6 +26,7 @@ X86MachineFunctionInfo.cpp X86PadShortFunction.cpp X86RegisterInfo.cpp + X86RegUsageInfoPropagate.cpp X86SelectionDAGInfo.cpp X86ShuffleDecodeConstantPool.cpp X86Subtarget.cpp Index: lib/Target/X86/X86.h =================================================================== --- lib/Target/X86/X86.h +++ lib/Target/X86/X86.h @@ -83,6 +83,11 @@ /// the upper portions of registers, and to save code size. FunctionPass *createX86FixupBWInsts(); +/// Return a MachineFunction pass that identifies call site +/// and propagates register usage information of callee to caller +/// if available with PysicalRegisterUsageInfo pass. +FunctionPass *createRegUsageInfoPropPass(); + void initializeFixupBWInstPassPass(PassRegistry &); } // End llvm namespace Index: lib/Target/X86/X86RegUsageInfoPropagate.cpp =================================================================== --- /dev/null +++ lib/Target/X86/X86RegUsageInfoPropagate.cpp @@ -0,0 +1,140 @@ +//=- X86RegUsageInfoPropagate.cpp - Target Specific Register Usage Informartion +//Propagation -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This pass is last required pass to get Interprocedural Register Allocation +// effect. +// See other two passes at lib/CodeGen/PhysicalRegisterUsageInfo.cpp and +// lib/CodeGen/RegUsageInfoCollector.cpp +// +// This pass iterates through MachineInstr in given MachineFunction and at each +// callsite quires PhysicalRegisterUsageInfo.cpp +// for RegMask (calculated based on actual register allocation) of callee +// function, if such details found then pass will update +// RegMask in call instruction. This updated RegMask will be used RegAllocators +// while allocating current MachineFunction. +// +//===----------------------------------------------------------------------===// + +#include "X86.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h" +#include "llvm/PassAnalysisSupport.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include +#include + +namespace llvm { +void initializeRegUsageInfoPropagationPassPass(PassRegistry &); +} + +using namespace llvm; + +#define DEBUG_TYPE "ipra" + +namespace { +class RegUsageInfoPropagationPass : public MachineFunctionPass { + +public: + RegUsageInfoPropagationPass() : MachineFunctionPass(ID) { + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeRegUsageInfoPropagationPassPass(Registry); + } + + const char *getPassName() const override { + return "X86 Register Usage Information Propagation"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; + + static char ID; + +private: + static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) { + for (MachineOperand &MO : MI.operands()) { + if (MO.isRegMask()) + MO.setRegMask(RegMask); + } + } +}; +} +char RegUsageInfoPropagationPass::ID = 0; + +INITIALIZE_PASS_BEGIN(RegUsageInfoPropagationPass, + "RegUsageInfoPropagationPass", + "X86 Register Usage Information Propagation", false, + false) +INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo) +INITIALIZE_PASS_END(RegUsageInfoPropagationPass, "RegUsageInfoPropagationPass", + "X86 Register Usage Information Propagation", false, false) + +FunctionPass *llvm::createRegUsageInfoPropPass() { + return new RegUsageInfoPropagationPass(); +} + +void RegUsageInfoPropagationPass::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) { + PhysicalRegisterUsageInfo *PRUI = &getAnalysis(); + + DEBUG(dbgs() << " ++++++++++++++++++++ Register Usage Info Propagation Pass " + "++++++++++++++++++++ \n"); + DEBUG(dbgs() << "MachineFunction : " << MF.getName() << "\n"); + + bool changed = false; + + for (auto &MBB : MF) { + for (auto &MI : MBB) { + // is it a call instr ? + if (MI.isCall()) { + DEBUG( + dbgs() + << "Call Instrunction Before Register Usage Info Propagation : \n"); + DEBUG(MI.print(dbgs())); + DEBUG(dbgs() << "\n"); + + auto updateRegMask = [&](StringRef FuncName) { + const auto *RegMask = PRUI->getRegUsageInfo(FuncName); + if (RegMask) { // else skip optimization + setRegMask(MI, &(*RegMask)[0]); + changed = true; + } + }; + + MachineOperand &Operand = MI.getOperand(0); + if (Operand.isGlobal()) { + updateRegMask(Operand.getGlobal()->getName()); + } else if (Operand.isSymbol()) { + updateRegMask(Operand.getSymbolName()); + } + + DEBUG( + dbgs() + << "Call Instrunction After Register Usage Info Propagation : \n"); + DEBUG(MI.print(dbgs())); + DEBUG(dbgs() << "\n"); + } + } + } + + DEBUG(dbgs() << " +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++" + "++++++ \n"); + return changed; +} Index: lib/Target/X86/X86TargetMachine.cpp =================================================================== --- lib/Target/X86/X86TargetMachine.cpp +++ lib/Target/X86/X86TargetMachine.cpp @@ -25,9 +25,11 @@ #include "llvm/Target/TargetOptions.h" using namespace llvm; -static cl::opt EnableMachineCombinerPass("x86-machine-combiner", - cl::desc("Enable the machine combiner pass"), - cl::init(true), cl::Hidden); +static cl::opt + EnableMachineCombinerPass("x86-machine-combiner", + cl::desc("Enable the machine combiner pass"), + cl::init(true), cl::Hidden); +extern cl::opt UseIPRA; namespace llvm { void initializeWinEHStatePassPass(PassRegistry &); @@ -224,9 +226,9 @@ // Command line options for x86 //===----------------------------------------------------------------------===// static cl::opt -UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, - cl::desc("Minimize AVX to SSE transition penalty"), - cl::init(true)); + UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, + cl::desc("Minimize AVX to SSE transition penalty"), + cl::init(true)); //===----------------------------------------------------------------------===// // X86 TTI query. @@ -238,7 +240,6 @@ }); } - //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// @@ -248,7 +249,7 @@ class X86PassConfig : public TargetPassConfig { public: X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) {} X86TargetMachine &getX86TargetMachine() const { return getTM(); @@ -279,6 +280,9 @@ // Install an instruction selector. addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); + if (UseIPRA) + addPass(createRegUsageInfoPropPass()); + // For ELF, cleanup any local-dynamic TLS accesses. if (TM->getTargetTriple().isOSBinFormatELF() && getOptLevel() != CodeGenOpt::None)