Index: lib/Target/AMDGPU/SIInsertWaits.cpp
===================================================================
--- lib/Target/AMDGPU/SIInsertWaits.cpp
+++ lib/Target/AMDGPU/SIInsertWaits.cpp
@@ -258,12 +258,6 @@
   // operand comes before the value operand and it may have
   // multiple data operands.
 
-  if (TII->isDS(MI) || TII->isFLAT(MI)) {
-    MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::data);
-    if (Data && Op.isIdenticalTo(*Data))
-      return true;
-  }
-
   if (TII->isDS(MI)) {
     MachineOperand *Data0 = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
     if (Data0 && Op.isIdenticalTo(*Data0))
@@ -273,6 +267,12 @@
     return Data1 && Op.isIdenticalTo(*Data1);
   }
 
+  if (TII->isFLAT(MI)) {
+    MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::vdata);
+    if (Data && Op.isIdenticalTo(*Data))
+      return true;
+  }
+
   // NOTE: This assumes that the value operand is before the
   // address operand, and that there is only one value operand.
   for (MachineInstr::mop_iterator I = MI.operands_begin(),
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -3107,9 +3107,9 @@
 
 multiclass FLAT_Load_Helper <flat op, string asm_name,
     RegisterClass regClass,
-    dag outs = (outs regClass:$vdst),
-    dag ins = (ins VReg_64:$addr, glc:$glc, slc:$slc, tfe:$tfe),
-    string asm = asm_name#" $vdst, $addr$glc$slc$tfe"> {
+    dag outs = (outs regClass:$vdata),
+    dag ins = (ins VReg_64:$vaddr, glc:$glc, slc:$slc, tfe:$tfe),
+    string asm = asm_name#" $vdata, $vaddr$glc$slc$tfe"> {
 
   let data = 0, mayLoad = 1 in {
 
@@ -3124,9 +3124,9 @@
 multiclass FLAT_Store_Helper <flat op, string asm_name,
     RegisterClass vdataClass,
     dag outs = (outs),
-    dag ins = (ins VReg_64:$addr, vdataClass:$data, glc:$glc,
+    dag ins = (ins VReg_64:$vaddr, vdataClass:$vdata, glc:$glc,
                    slc:$slc, tfe:$tfe),
-    string asm = asm_name#" $addr, $data$glc$slc$tfe"> {
+    string asm = asm_name#" $vaddr, $vdata$glc$slc$tfe"> {
 
   let mayLoad = 0, mayStore = 1, vdst = 0 in {
 
@@ -3141,30 +3141,30 @@
 multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc,
     RegisterClass data_rc = vdst_rc,
     dag outs_noret = (outs),
-    string asm_noret = asm_name#" $addr, $data"#"$slc"#"$tfe"> {
+    string asm_noret = asm_name#" $vaddr, $vdata"#"$slc"#"$tfe"> {
 
   let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0 in {
     def "" : FLAT_Pseudo <NAME, outs_noret,
-                          (ins VReg_64:$addr, data_rc:$data,
+                          (ins VReg_64:$vaddr, data_rc:$vdata,
                                slc:$slc, tfe:$tfe), []>,
              AtomicNoRet <NAME, 0>;
 
     def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret,
-                            (ins VReg_64:$addr, data_rc:$data,
+                            (ins VReg_64:$vaddr, data_rc:$vdata,
                                  slc:$slc, tfe:$tfe),
                             asm_noret>;
 
     def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret,
-                            (ins VReg_64:$addr, data_rc:$data,
+                            (ins VReg_64:$vaddr, data_rc:$vdata,
                                  slc:$slc, tfe:$tfe),
                             asm_noret>;
   }
 
   let glc = 1, hasPostISelHook = 1 in {
-    defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst),
-                        (ins VReg_64:$addr, data_rc:$data, slc:$slc,
+    defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdata),
+                        (ins VReg_64:$vaddr, data_rc:$vdata_in, slc:$slc,
                              tfe:$tfe),
-                        asm_name#" $vdst, $addr, $data glc$slc$tfe", []>;
+                        asm_name#" $vdata, $vaddr, $vdata_in glc$slc$tfe", []>;
   }
 }