Index: lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.h +++ lib/Target/AMDGPU/SIInstrInfo.h @@ -157,6 +157,9 @@ MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; + bool ReverseBranchCondition( + SmallVectorImpl &Cond) const override; + bool areMemAccessesTriviallyDisjoint( MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA = nullptr) const override; Index: lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.cpp +++ lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1166,6 +1166,13 @@ return 2; } +bool SIInstrInfo::ReverseBranchCondition( + SmallVectorImpl &Cond) const { + assert(Cond.size() == 1); + Cond[0].setImm(-Cond[0].getImm()); + return false; +} + static void removeModOperands(MachineInstr &MI) { unsigned Opc = MI.getOpcode(); int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc, Index: test/CodeGen/AMDGPU/uniform-cfg.ll =================================================================== --- test/CodeGen/AMDGPU/uniform-cfg.ll +++ test/CodeGen/AMDGPU/uniform-cfg.ll @@ -168,10 +168,8 @@ ; SI-LABEL: {{^}}uniform_if_else_ret: ; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 -; SI-NEXT: s_cbranch_scc1 [[ELSE_LABEL:[0-9_A-Za-z]+]] -; SI-NEXT: s_branch [[IF_LABEL:[0-9_A-Za-z]+]] +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] -; SI: [[ELSE_LABEL]]: ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; SI: buffer_store_dword [[TWO]] ; SI: s_endpgm @@ -199,10 +197,8 @@ ; SI-LABEL: {{^}}uniform_if_else: ; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 -; SI-NEXT: s_cbranch_scc1 [[ELSE_LABEL:[0-9_A-Za-z]+]] -; SI-NEXT: s_branch [[IF_LABEL:[0-9_A-Za-z]+]] +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] -; SI: [[ELSE_LABEL]]: ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; SI: buffer_store_dword [[TWO]] ; SI: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]