Index: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp @@ -601,7 +601,6 @@ class IAPrinter { std::vector Conds; std::map> OpMap; - SmallVector ReqFeatures; std::string Result; std::string AsmString; @@ -648,7 +647,7 @@ } void print(raw_ostream &O) { - if (Conds.empty() && ReqFeatures.empty()) { + if (Conds.empty()) { O.indent(6) << "return true;\n"; return; } @@ -798,6 +797,18 @@ IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); + std::string Namespace = Target.getName(); + std::vector ReqFeatures; + if (PassSubtarget) { + // We only consider ReqFeatures predicates if PassSubtarget + std::vector RF = + CGA.TheDef->getValueAsListOfDefs("Predicates"); + std::copy_if(RF.begin(), RF.end(), std::back_inserter(ReqFeatures), + [](Record *R) { + return R->getValueAsBit("AssemblerMatcherPredicate"); + }); + } + unsigned NumMIOps = 0; for (auto &Operand : CGA.ResultOperands) NumMIOps += Operand.getMINumOperands(); @@ -902,6 +913,27 @@ } if (CantHandle) continue; + + for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) { + Record *R = *I; + std::string AsmCondString = R->getValueAsString("AssemblerCondString"); + + // AsmCondString has syntax [!]F(,[!]F)* + SmallVector Ops; + SplitString(AsmCondString, Ops, ","); + assert(!Ops.empty() && "AssemblerCondString cannot be empty"); + + for (auto &Op : Ops) { + assert(!Op.empty() && "Empty operator"); + if (Op[0] == '!') + Cond = "!STI.getFeatureBits()[" + Namespace + "::" + + Op.substr(1).str() + "]"; + else + Cond = "STI.getFeatureBits()[" + Namespace + "::" + Op.str() + "]"; + IAP.addCond(Cond); + } + } + IAPrinterMap[Aliases.first].push_back(std::move(IAP)); } }