Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -910,6 +910,8 @@
 
   void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
 
+  void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
+
   /// EmitFuncArgumentDbgValue - If V is an function argument then create
   /// corresponding DBG_VALUE machine instruction for it now. At the end of
   /// instruction selection, they will be inserted to the entry BB.
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6790,10 +6790,9 @@
       // Copy the output from the appropriate register.  Find a register that
       // we can use.
       if (OpInfo.AssignedRegs.Regs.empty()) {
-        LLVMContext &Ctx = *DAG.getContext();
-        Ctx.emitError(CS.getInstruction(),
-                      "couldn't allocate output register for constraint '" +
-                          Twine(OpInfo.ConstraintCode) + "'");
+        emitInlineAsmError(
+            CS, "couldn't allocate output register for constraint '" +
+                    Twine(OpInfo.ConstraintCode) + "'");
         return;
       }
 
@@ -6846,10 +6845,9 @@
           // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
           if (OpInfo.isIndirect) {
             // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
-            LLVMContext &Ctx = *DAG.getContext();
-            Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
-                                               " don't know how to handle tied "
-                                               "indirect register inputs");
+            emitInlineAsmError(CS, "inline asm not supported yet:"
+                                   " don't know how to handle tied "
+                                   "indirect register inputs");
             return;
           }
 
@@ -6863,10 +6861,9 @@
             if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
               MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
             else {
-              LLVMContext &Ctx = *DAG.getContext();
-              Ctx.emitError(CS.getInstruction(),
-                            "inline asm error: This value"
-                            " type register class is not natively supported!");
+              emitInlineAsmError(
+                  CS, "inline asm error: This value"
+                      " type register class is not natively supported!");
               return;
             }
           }
@@ -6904,10 +6901,8 @@
         TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
                                           Ops, DAG);
         if (Ops.empty()) {
-          LLVMContext &Ctx = *DAG.getContext();
-          Ctx.emitError(CS.getInstruction(),
-                        "invalid operand for inline asm constraint '" +
-                            Twine(OpInfo.ConstraintCode) + "'");
+          emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
+                                     Twine(OpInfo.ConstraintCode) + "'");
           return;
         }
 
@@ -6947,20 +6942,17 @@
 
       // TODO: Support this.
       if (OpInfo.isIndirect) {
-        LLVMContext &Ctx = *DAG.getContext();
-        Ctx.emitError(CS.getInstruction(),
-                      "Don't know how to handle indirect register inputs yet "
-                      "for constraint '" +
-                          Twine(OpInfo.ConstraintCode) + "'");
+        emitInlineAsmError(
+            CS, "Don't know how to handle indirect register inputs yet "
+                "for constraint '" +
+                    Twine(OpInfo.ConstraintCode) + "'");
         return;
       }
 
       // Copy the input into the appropriate registers.
       if (OpInfo.AssignedRegs.Regs.empty()) {
-        LLVMContext &Ctx = *DAG.getContext();
-        Ctx.emitError(CS.getInstruction(),
-                      "couldn't allocate input reg for constraint '" +
-                          Twine(OpInfo.ConstraintCode) + "'");
+        emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
+                                   Twine(OpInfo.ConstraintCode) + "'");
         return;
       }
 
@@ -7058,6 +7050,17 @@
   DAG.setRoot(Chain);
 }
 
+void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
+                                             const Twine &Message) {
+  LLVMContext &Ctx = *DAG.getContext();
+  Ctx.emitError(CS.getInstruction(), Message);
+
+  // Make sure we leave the DAG in a valid state
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType());
+  setValue(CS.getInstruction(), DAG.getUNDEF(VT));
+}
+
 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
   DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
                           MVT::Other, getRoot(),
Index: test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
===================================================================
--- test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
+++ test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=arm64 -exit-on-error < %s  2> %t
+; RUN: not llc -march=arm64 < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
Index: test/CodeGen/PowerPC/crbit-asm-disabled.ll
===================================================================
--- test/CodeGen/PowerPC/crbit-asm-disabled.ll
+++ test/CodeGen/PowerPC/crbit-asm-disabled.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -mcpu=pwr7 -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
+; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/vec-asm-disabled.ll
===================================================================
--- test/CodeGen/PowerPC/vec-asm-disabled.ll
+++ test/CodeGen/PowerPC/vec-asm-disabled.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -mcpu=pwr7 -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
+; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
===================================================================
--- test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
+++ test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -exit-on-error -o /dev/null %s 2>&1 | FileCheck %s
+; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s
 target triple = "x86_64--"
 
 ; CHECK: error: couldn't allocate output register for constraint '{ax}'