Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6794,6 +6794,8 @@ Ctx.emitError(CS.getInstruction(), "couldn't allocate output register for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; } @@ -6850,6 +6852,8 @@ Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" " don't know how to handle tied " "indirect register inputs"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; } @@ -6867,6 +6871,8 @@ Ctx.emitError(CS.getInstruction(), "inline asm error: This value" " type register class is not natively supported!"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; } } @@ -6908,6 +6914,8 @@ Ctx.emitError(CS.getInstruction(), "invalid operand for inline asm constraint '" + Twine(OpInfo.ConstraintCode) + "'"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; } @@ -6952,6 +6960,8 @@ "Don't know how to handle indirect register inputs yet " "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; } @@ -6961,6 +6971,8 @@ Ctx.emitError(CS.getInstruction(), "couldn't allocate input reg for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); + auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType()); + setValue(CS.getInstruction(), DAG.getUNDEF(VT)); return; }