Index: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td +++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td @@ -328,11 +328,11 @@ "Insert one nop instruction for each high level source statement" >; -def FeatureDebuggerReserveTrapRegs : SubtargetFeature< - "amdgpu-debugger-reserve-trap-regs", - "DebuggerReserveTrapVGPRs", +def FeatureDebuggerReserveRegs : SubtargetFeature< + "amdgpu-debugger-reserve-regs", + "DebuggerReserveRegs", "true", - "Reserve VGPRs for trap handler usage" + "Reserve registers for debugger usage" >; //===----------------------------------------------------------------------===// Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -435,12 +435,13 @@ MaxSGPR += ExtraSGPRs; - // Update necessary Reserved* fields and max VGPRs used if - // "amdgpu-debugger-reserve-trap-regs" attribute was specified. - if (STM.debuggerReserveTrapVGPRs()) { + // Record first reserved register and reserved register count fields, and + // update max register counts if "amdgpu-debugger-reserve-regs" attribute was + // specified. + if (STM.debuggerReserveRegs()) { ProgInfo.ReservedVGPRFirst = MaxVGPR + 1; - ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount(); - MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount(); + ProgInfo.ReservedVGPRCount = MFI->getDebuggerReservedVGPRCount(); + MaxVGPR += MFI->getDebuggerReservedVGPRCount(); } // We found the maximum register index. They start at 0, so add one to get the Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -96,7 +96,7 @@ unsigned IsaVersion; bool EnableSIScheduler; bool DebuggerInsertNops; - bool DebuggerReserveTrapVGPRs; + bool DebuggerReserveRegs; std::unique_ptr FrameLowering; std::unique_ptr TLInfo; @@ -319,8 +319,8 @@ return DebuggerInsertNops; } - bool debuggerReserveTrapVGPRs() const { - return DebuggerReserveTrapVGPRs; + bool debuggerReserveRegs() const { + return DebuggerReserveRegs; } bool dumpCode() const { Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -98,7 +98,7 @@ LDSBankCount(0), IsaVersion(ISAVersion0_0_0), EnableSIScheduler(false), - DebuggerInsertNops(false), DebuggerReserveTrapVGPRs(false), + DebuggerInsertNops(false), DebuggerReserveRegs(false), FrameLowering(nullptr), GISel(), InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) { Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -62,8 +62,8 @@ unsigned MaximumWorkGroupSize; - // Number of reserved VGPRs for trap handler usage. - unsigned DebuggerReserveTrapVGPRCount; + // Number of reserved VGPRs for debugger usage. + unsigned DebuggerReservedVGPRCount; public: // FIXME: Make private @@ -329,8 +329,9 @@ ReturnsVoid = Value; } - unsigned getDebuggerReserveTrapVGPRCount() const { - return DebuggerReserveTrapVGPRCount; + /// \returns Number of reserved VGPRs for debugger usage. + unsigned getDebuggerReservedVGPRCount() const { + return DebuggerReservedVGPRCount; } unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const; Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -49,7 +49,7 @@ PSInputAddr(0), ReturnsVoid(true), MaximumWorkGroupSize(0), - DebuggerReserveTrapVGPRCount(0), + DebuggerReservedVGPRCount(0), LDSWaveSpillSize(0), PSInputEna(0), NumUserSGPRs(0), @@ -134,8 +134,8 @@ else MaximumWorkGroupSize = ST.getWavefrontSize(); - if (ST.debuggerReserveTrapVGPRs()) - DebuggerReserveTrapVGPRCount = 4; + if (ST.debuggerReserveRegs()) + DebuggerReservedVGPRCount = 4; } unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer( Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -193,12 +193,12 @@ assert(!isSubRegister(ScratchRSrcReg, ScratchWaveOffsetReg)); } - // Reserve VGPRs for trap handler usage if "amdgpu-debugger-reserve-trap-regs" + // Reserve registers for debugger usage if "amdgpu-debugger-reserve-trap-regs" // attribute was specified. const AMDGPUSubtarget &ST = MF.getSubtarget(); - if (ST.debuggerReserveTrapVGPRs()) { + if (ST.debuggerReserveRegs()) { unsigned ReservedVGPRFirst = - MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount(); + MaxWorkGroupVGPRCount - MFI->getDebuggerReservedVGPRCount(); for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) { unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i); reserveRegisterTuples(Reserved, Reg); Index: llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll +++ llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll @@ -1,8 +1,6 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-trap-regs -verify-machineinstrs < %s | FileCheck %s - +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s ; CHECK: reserved_vgpr_first = {{[0-9]+}} ; CHECK-NEXT: reserved_vgpr_count = 4 - ; CHECK: ReservedVGPRFirst: {{[0-9]+}} ; CHECK-NEXT: ReservedVGPRCount: 4