Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1420,6 +1420,12 @@
       OutCC = changeIntCCToAArch64CC(CC);
     } else {
       assert(LHS.getValueType().isFloatingPoint());
+      // Also handle f16, for which we need to do a f32 comparison.
+      if (LHS.getValueType() == MVT::f16) {
+        LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
+        RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
+      }
+
       AArch64CC::CondCode ExtraCC;
       changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
       // Some floating point conditions can't be tested with a single condition
Index: test/CodeGen/AArch64/half.ll
===================================================================
--- test/CodeGen/AArch64/half.ll
+++ test/CodeGen/AArch64/half.ll
@@ -81,3 +81,16 @@
   store half %val16, half* %addr
   ret void
 }
+
+define i16 @test_fccmp(i1 %a) {
+;CHECK-LABEL: test_fccmp:
+;CHECK: fcmp
+;CHECK: fccmp
+  %cmp0 = fcmp ogt half 0xH3333, undef
+  %cmp1 = fcmp ogt half 0xH2222, undef
+  %x = select i1 %cmp0, i16 0, i16 undef
+  %or = or i1 %cmp1, %cmp0
+  %y = select i1 %or, i16 4, i16 undef
+  %r = add i16 %x, %y
+  ret i16 %r
+}