Index: llvm/trunk/lib/Target/Sparc/LeonFeatures.td =================================================================== --- llvm/trunk/lib/Target/Sparc/LeonFeatures.td +++ llvm/trunk/lib/Target/Sparc/LeonFeatures.td @@ -0,0 +1,24 @@ +//===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + + +//===----------------------------------------------------------------------===// +// UMAC and SMAC support for LEON3 and LEON4 processors. +//===----------------------------------------------------------------------===// + +//support to casa instruction; for leon3 subtarget only +def UMACSMACSupport : SubtargetFeature< + "hasumacsmac", + "HasUmacSmac", + "true", + "Enable UMAC and SMAC for LEON3 and LEON4 processors" +>; Index: llvm/trunk/lib/Target/Sparc/Sparc.td =================================================================== --- llvm/trunk/lib/Target/Sparc/Sparc.td +++ llvm/trunk/lib/Target/Sparc/Sparc.td @@ -46,6 +46,9 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", "Use the popc (population count) instruction">; +//==== Features added predmoninantly for LEON subtarget support +include "LeonFeatures.td" + //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// @@ -111,26 +114,26 @@ // LEON 3 FT generic def : Processor<"leon3", LEON3Itineraries, - [FeatureLeon]>; + [FeatureLeon, UMACSMACSupport]>; // LEON 3 FT (UT699) // TO DO: Place-holder: Processor specific features will be added *very* soon here. def : Processor<"ut699", LEON3Itineraries, - [FeatureLeon]>; + [FeatureLeon, UMACSMACSupport]>; // LEON3 FT (GR712RC) // TO DO: Place-holder: Processor specific features will be added *very* soon here. def : Processor<"gr712rc", LEON3Itineraries, - [FeatureLeon]>; + [FeatureLeon, UMACSMACSupport]>; // LEON 4 FT generic def : Processor<"leon4", LEON4Itineraries, - [FeatureLeon]>; + [FeatureLeon, UMACSMACSupport]>; // LEON 4 FT (GR740) // TO DO: Place-holder: Processor specific features will be added *very* soon here. def : Processor<"gr740", LEON4Itineraries, - [FeatureLeon]> {} + [FeatureLeon, UMACSMACSupport]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing Index: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td @@ -49,6 +49,10 @@ // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; +// HasUMAC_SMAC - This is true when the target processor supports the +// UMAC and SMAC instructions +def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; + // UseDeprecatedInsts - This predicate is true when the target processor is a // V8, or when it is V9 but the V8 deprecated instructions are efficient enough // to use when appropriate. In either of these cases, the instruction selector @@ -1502,6 +1506,30 @@ [(set i32:$rd, (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>; +// TODO: Add DAG sequence to lower these instructions. Currently, only provided +// as inline assembler-supported instructions. +let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { + def SMACrr : F3_1<2, 0b111111, + (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), + "smac $rs1, $rs2, $rd", + [], IIC_smac_umac>; + + def SMACri : F3_2<2, 0b111111, + (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), + "smac $rs1, $simm13, $rd", + [], IIC_smac_umac>; + + def UMACrr : F3_1<2, 0b111110, + (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), + "umac $rs1, $rs2, $rd", + [], IIC_smac_umac>; + + def UMACri : F3_2<2, 0b111110, + (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), + "umac $rs1, $simm13, $rd", + [], IIC_smac_umac>; +} + let Defs = [ICC] in { defm TADDCC : F3_12np<"taddcc", 0b100000>; defm TSUBCC : F3_12np<"tsubcc", 0b100001>; Index: llvm/trunk/lib/Target/Sparc/SparcSchedule.td =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSchedule.td +++ llvm/trunk/lib/Target/Sparc/SparcSchedule.td @@ -32,6 +32,7 @@ def IIC_fpu_abs : InstrItinClass; def IIC_fpu_movs : InstrItinClass; def IIC_fpu_negs : InstrItinClass; +def IIC_smac_umac : InstrItinClass; def IIC_fpu_stod : InstrItinClass; def LEONIU : FuncUnit; // integer unit @@ -79,6 +80,7 @@ InstrItinData], [1, 1]>, InstrItinData], [4, 1]>, InstrItinData], [35, 1]>, + InstrItinData], [2, 1]>, InstrItinData], [5, 1]>, InstrItinData], [3, 1]>, InstrItinData], [4, 1]>, @@ -106,6 +108,7 @@ InstrItinData], [1, 1]>, InstrItinData], [4, 1]>, InstrItinData], [35, 1]>, + InstrItinData], [2, 1]>, InstrItinData], [5, 1]>, InstrItinData], [3, 1]>, InstrItinData], [4, 1]>, Index: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h @@ -34,6 +34,7 @@ virtual void anchor(); bool IsV9; bool IsLeon; + bool HasUmacSmac; bool V8DeprecatedInsts; bool IsVIS, IsVIS2, IsVIS3; bool Is64Bit; @@ -66,6 +67,7 @@ bool isV9() const { return IsV9; } bool isLeon() const { return IsLeon; } + bool hasUmacSmac() const { return HasUmacSmac; } bool isVIS() const { return IsVIS; } bool isVIS2() const { return IsVIS2; } bool isVIS3() const { return IsVIS3; } Index: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp @@ -29,10 +29,12 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { IsV9 = false; + IsLeon = false; V8DeprecatedInsts = false; IsVIS = false; HasHardQuad = false; UsePopc = false; + HasUmacSmac = false; // Determine default and user specified characteristics std::string CPUName = CPU; Index: llvm/trunk/test/MC/Sparc/leon-instructions.s =================================================================== --- llvm/trunk/test/MC/Sparc/leon-instructions.s +++ llvm/trunk/test/MC/Sparc/leon-instructions.s @@ -0,0 +1,12 @@ +! RUN: llvm-mc %s -arch=sparc -mcpu=leon3 -show-encoding | FileCheck %s +! RUN: llvm-mc %s -arch=sparc -mcpu=ut699 -show-encoding | FileCheck %s +! RUN: llvm-mc %s -arch=sparc -mcpu=gr712rc -show-encoding | FileCheck %s +! RUN: llvm-mc %s -arch=sparc -mcpu=leon4 -show-encoding | FileCheck %s +! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s + + + ! CHECK: umac %i0, %l6, %o2 ! encoding: [0x95,0xf6,0x00,0x16] + umac %i0, %l6, %o2 + + ! CHECK: smac %i0, %l6, %o2 ! encoding: [0x95,0xfe,0x00,0x16] + smac %i0, %l6, %o2