Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -236,6 +236,7 @@ // beq $r0, $zero, $L2 => beqz $r0, $L2 return isReg(MI, 1) && printAlias("beqz", MI, 0, 2, OS); case Mips::BNE: + case Mips::BNE_MM: // bne $r0, $zero, $L2 => bnez $r0, $L2 return isReg(MI, 1) && printAlias("bnez", MI, 0, 2, OS); case Mips::BNE64: Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -1047,6 +1047,15 @@ def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>; +defm : BrcondPats; + +defm : SeteqPats; +defm : SetlePats; +defm : SetgtPats; +defm : SetgePats; +defm : SetgeImmPats; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// @@ -1080,6 +1089,12 @@ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"slt $rs, $rt, $imm", + (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; + def : MipsInstAlias<"sltu $rs, $rt, $imm", + (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", @@ -1115,4 +1130,8 @@ (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; def : MipsInstAlias<"not $rt, $rs", (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"bnez $rs,$offset", + (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"beqz $rs,$offset", + (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; } Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -535,23 +535,24 @@ def : WrapperPat; def : WrapperPat; def : WrapperPat; -} -defm : BrcondPats; + defm : BrcondPats; +} def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), (BLEZ64 i64:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), (BGEZ64 i64:$lhs, bb:$dst)>; +let AdditionalPredicates = [NotInMicroMips] in { // setcc patterns -defm : SeteqPats; -defm : SetlePats; -defm : SetgtPats; -defm : SetgePats; -defm : SetgeImmPats; - + defm : SeteqPats; + defm : SetlePats; + defm : SetgtPats; + defm : SetgePats; + defm : SetgeImmPats; +} // truncate def : MipsPat<(trunc (assertsext GPR64:$src)), (EXTRACT_SUBREG GPR64:$src, sub_32)>; Index: lib/Target/Mips/MipsInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsInstrInfo.cpp +++ lib/Target/Mips/MipsInstrInfo.cpp @@ -268,7 +268,9 @@ if (Subtarget.inMicroMipsMode()) { switch (Opcode) { case Mips::BNE: + case Mips::BNE_MM: case Mips::BEQ: + case Mips::BEQ_MM: // microMIPS has NE,EQ branches that do not have delay slots provided one // of the operands is zero. if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) @@ -301,12 +303,14 @@ case Mips::BAL: return Mips::BALC; case Mips::BEQ: + case Mips::BEQ_MM: if (canUseShortMicroMipsCTI) return Mips::BEQZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) return 0; return Mips::BEQC; case Mips::BNE: + case Mips::BNE_MM: if (canUseShortMicroMipsCTI) return Mips::BNEZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1686,33 +1686,35 @@ } def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; -def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xa>; -def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xb>; +let AdditionalPredicates = [NotInMicroMips] in { + def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xa>; + def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xb>; +} def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { -/// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM<0, 0x21>; -def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM<0, 0x23>; + /// Arithmetic Instructions (3-Operand, R-Type) + def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, + ADD_FM<0, 0x21>; + def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, + ADD_FM<0, 0x23>; } let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>; def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>; -def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; -def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; let AdditionalPredicates = [NotInMicroMips] in { -def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, - ADD_FM<0, 0x24>; -def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, - ADD_FM<0, 0x25>; -def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, - ADD_FM<0, 0x26>; -def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; + def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; + def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; + def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, + ADD_FM<0, 0x24>; + def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, + ADD_FM<0, 0x25>; + def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, + ADD_FM<0, 0x26>; + def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; } /// Shift Instructions @@ -2223,13 +2225,13 @@ (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; def : MipsInstAlias<"negu $rt, $rs", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; -def : MipsInstAlias< +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias< "slt $rs, $rt, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias< "and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; @@ -2558,38 +2560,39 @@ def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; // brcond patterns -multiclass BrcondPats { +multiclass BrcondPats { def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond RC:$cond, bb:$dst), (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } - -defm : BrcondPats; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : BrcondPats; +} def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), (BLEZ i32:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), @@ -2608,11 +2611,12 @@ (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; } -multiclass SetlePats { +multiclass SetlePats { def : MipsPat<(setle RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>; def : MipsPat<(setule RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>; } multiclass SetgtPats { @@ -2622,26 +2626,29 @@ (SLTuOp RC:$rhs, RC:$lhs)>; } -multiclass SetgePats { +multiclass SetgePats { def : MipsPat<(setge RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>; } -multiclass SetgeImmPats { +multiclass SetgeImmPats { def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } -defm : SeteqPats; -defm : SetlePats; -defm : SetgtPats; -defm : SetgePats; -defm : SetgeImmPats; +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats; + defm : SetlePats; + defm : SetgtPats; + defm : SetgePats; + defm : SetgeImmPats; +} // bswap pattern def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -408,7 +408,9 @@ switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BEQ: return Mips::BNE; + case Mips::BEQ_MM: return Mips::BNE_MM; case Mips::BNE: return Mips::BEQ; + case Mips::BNE_MM: return Mips::BEQ_MM; case Mips::BGTZ: return Mips::BLEZ; case Mips::BGEZ: return Mips::BLTZ; case Mips::BLTZ: return Mips::BGEZ; @@ -506,16 +508,17 @@ } unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { - return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || - Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || - Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || - Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || - Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || - Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || - Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || - Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC || - Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC || + return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || + Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || + Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || + Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || + Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || + Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || + Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || + Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || + Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || + Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC || + Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BC) ? Opc : 0; } Index: test/CodeGen/Mips/brconlt.ll =================================================================== --- test/CodeGen/Mips/brconlt.ll +++ test/CodeGen/Mips/brconlt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 @@ -12,9 +13,10 @@ %cmp = icmp slt i32 %0, %1 br i1 %cmp, label %if.end, label %if.then -; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]] -; 16: $[[LABEL]]: +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]] +; 16: $[[LABEL]]: if.then: ; preds = %entry store i32 1, i32* @result, align 4 Index: test/CodeGen/Mips/setcc-se.ll =================================================================== --- test/CodeGen/Mips/setcc-se.ll +++ test/CodeGen/Mips/setcc-se.ll @@ -1,9 +1,12 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6 @g1 = external global i32 ; CHECK-LABEL: seteq0: -; CHECK: sltiu ${{[0-9]+}}, $4, 1 +; CHECK: sltiu ${{[0-9]+}}, $4, 1 +; MMR6: sltiu ${{[0-9]+}}, $4, 1 +; MMR6: