Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -236,6 +236,7 @@ // beq $r0, $zero, $L2 => beqz $r0, $L2 return isReg(MI, 1) && printAlias("beqz", MI, 0, 2, OS); case Mips::BNE: + case Mips::BNE_MM: // bne $r0, $zero, $L2 => bnez $r0, $L2 return isReg(MI, 1) && printAlias("bnez", MI, 0, 2, OS); case Mips::BNE64: Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -1037,6 +1037,54 @@ def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>; +// brcond patterns +multiclass BrcondPats_MM { + def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), + (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; + def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), + (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; + + def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ_MM (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ_MM (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQ_MM (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQ_MM (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), + (BEQ_MM (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), + (BEQ_MM (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + + def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ_MM (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ_MM (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + + def : MipsPat<(brcond RC:$cond, bb:$dst), + (BNEOp RC:$cond, ZEROReg, bb:$dst)>; +} + +multiclass SetgeImmPats_MM { + def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), + (XORi_MM (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; + def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), + (XORi_MM (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; +} + + defm : BrcondPats_MM; + + defm : SeteqPats; + defm : SetlePats; + defm : SetgtPats; + defm : SetgePats; + defm : SetgeImmPats_MM; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// @@ -1070,6 +1118,12 @@ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"slt $rs, $rt, $imm", + (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; + def : MipsInstAlias<"sltu $rs, $rt, $imm", + (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", @@ -1105,4 +1159,8 @@ (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; def : MipsInstAlias<"not $rt, $rs", (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"bnez $rs,$offset", + (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"beqz $rs,$offset", + (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; } Index: lib/Target/Mips/MipsInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsInstrInfo.cpp +++ lib/Target/Mips/MipsInstrInfo.cpp @@ -268,7 +268,9 @@ if (Subtarget.inMicroMipsMode()) { switch (Opcode) { case Mips::BNE: + case Mips::BNE_MM: case Mips::BEQ: + case Mips::BEQ_MM: // microMIPS has NE,EQ branches that do not have delay slots provided one // of the operands is zero. if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) @@ -301,12 +303,14 @@ case Mips::BAL: return Mips::BALC; case Mips::BEQ: + case Mips::BEQ_MM: if (canUseShortMicroMipsCTI) return Mips::BEQZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) return 0; return Mips::BEQC; case Mips::BNE: + case Mips::BNE_MM: if (canUseShortMicroMipsCTI) return Mips::BNEZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1686,33 +1686,34 @@ } def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; -def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xa>; -def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xb>; -def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { -/// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM<0, 0x21>; -def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM<0, 0x23>; + def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xa>; + def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xb>; + def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; + + /// Arithmetic Instructions (3-Operand, R-Type) + def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, + ADD_FM<0, 0x21>; + def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, + ADD_FM<0, 0x23>; } let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>; def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>; -def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; -def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; let AdditionalPredicates = [NotInMicroMips] in { -def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, - ADD_FM<0, 0x24>; -def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, - ADD_FM<0, 0x25>; -def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, - ADD_FM<0, 0x26>; -def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; + def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; + def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; + def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, + ADD_FM<0, 0x24>; + def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, + ADD_FM<0, 0x25>; + def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, + ADD_FM<0, 0x26>; + def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; } /// Shift Instructions @@ -2222,13 +2223,13 @@ (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; def : MipsInstAlias<"negu $rt, $rs", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; -def : MipsInstAlias< +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias< "slt $rs, $rt, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias< "and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; @@ -2257,14 +2258,15 @@ def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>; let AdditionalPredicates = [NotInMicroMips] in { -def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; + + def : MipsInstAlias<"bnez $rs,$offset", + (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"beqz $rs,$offset", + (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; } -def : MipsInstAlias<"bnez $rs,$offset", - (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"bnezl $rs,$offset", (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; -def : MipsInstAlias<"beqz $rs,$offset", - (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"beqzl $rs,$offset", (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; let AdditionalPredicates = [NotInMicroMips] in { @@ -2586,9 +2588,9 @@ def : MipsPat<(brcond RC:$cond, bb:$dst), (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } - -defm : BrcondPats; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : BrcondPats; +} def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), (BLEZ i32:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), @@ -2636,11 +2638,13 @@ (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } -defm : SeteqPats; -defm : SetlePats; -defm : SetgtPats; -defm : SetgePats; -defm : SetgeImmPats; +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats; + defm : SetlePats; + defm : SetgtPats; + defm : SetgePats; + defm : SetgeImmPats; +} // bswap pattern def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -408,7 +408,9 @@ switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BEQ: return Mips::BNE; + case Mips::BEQ_MM: return Mips::BNE_MM; case Mips::BNE: return Mips::BEQ; + case Mips::BNE_MM: return Mips::BEQ_MM; case Mips::BGTZ: return Mips::BLEZ; case Mips::BGEZ: return Mips::BLTZ; case Mips::BLTZ: return Mips::BGEZ; @@ -506,16 +508,17 @@ } unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { - return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || - Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || - Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || - Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || - Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || - Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || - Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || - Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC || - Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC || + return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || + Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || + Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || + Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || + Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || + Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || + Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || + Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || + Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || + Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC || + Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BC) ? Opc : 0; } Index: test/CodeGen/Mips/brconlt.ll =================================================================== --- test/CodeGen/Mips/brconlt.ll +++ test/CodeGen/Mips/brconlt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 @@ -13,6 +14,7 @@ br i1 %cmp, label %if.end, label %if.then ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]] ; 16: $[[LABEL]]: Index: test/CodeGen/Mips/setcc-se.ll =================================================================== --- test/CodeGen/Mips/setcc-se.ll +++ test/CodeGen/Mips/setcc-se.ll @@ -1,9 +1,12 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6 @g1 = external global i32 ; CHECK-LABEL: seteq0: ; CHECK: sltiu ${{[0-9]+}}, $4, 1 +; MMR6: sltiu ${{[0-9]+}}, $4, 1 +; MMR6: SLTiu_MM define i32 @seteq0(i32 %a) { entry: @@ -14,6 +17,8 @@ ; CHECK-LABEL: setne0: ; CHECK: sltu ${{[0-9]+}}, $zero, $4 +; MMR6: sltu ${{[0-9]+}}, $zero, $4 +; MMR6: SLTu_MM define i32 @setne0(i32 %a) { entry: @@ -24,6 +29,8 @@ ; CHECK-LABEL: slti_beq0: ; CHECK: slti $[[R0:[0-9]+]], $4, -32768 +; MMR6: slti $[[R0:[0-9]+]], $4, -32768 +; MMR6: SLTi_MM ; CHECK: beqz $[[R0]] define void @slti_beq0(i32 %a) { @@ -41,6 +48,8 @@ ; CHECK-LABEL: slti_beq1: ; CHECK: slt ${{[0-9]+}} +; MMR6: slt ${{[0-9]+}} +; MMR6: SLT_MM define void @slti_beq1(i32 %a) { entry: @@ -57,6 +66,8 @@ ; CHECK-LABEL: slti_beq2: ; CHECK: slti $[[R0:[0-9]+]], $4, 32767 +; MMR6: slti $[[R0:[0-9]+]], $4, 32767 +; MMR6: SLTi_MM ; CHECK: beqz $[[R0]] define void @slti_beq2(i32 %a) { @@ -74,6 +85,8 @@ ; CHECK-LABEL: slti_beq3: ; CHECK: slt ${{[0-9]+}} +; MMR6: slt ${{[0-9]+}} +; MMR6: SLT_MM define void @slti_beq3(i32 %a) { entry: @@ -90,6 +103,8 @@ ; CHECK-LABEL: sltiu_beq0: ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767 +; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767 +; MMR6: SLTiu_MM ; CHECK: beqz $[[R0]] define void @sltiu_beq0(i32 %a) { @@ -107,6 +122,8 @@ ; CHECK-LABEL: sltiu_beq1: ; CHECK: sltu ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}} +; MMR6: SLTu_MM define void @sltiu_beq1(i32 %a) { entry: @@ -123,6 +140,8 @@ ; CHECK-LABEL: sltiu_beq2: ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768 +; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768 +; MMR6: SLTiu_MM ; CHECK: beqz $[[R0]] define void @sltiu_beq2(i32 %a) { @@ -140,6 +159,8 @@ ; CHECK-LABEL: sltiu_beq3: ; CHECK: sltu ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}} +; MMR6: SLTu_MM define void @sltiu_beq3(i32 %a) { entry: Index: test/CodeGen/Mips/seteq.ll =================================================================== --- test/CodeGen/Mips/seteq.ll +++ test/CodeGen/Mips/seteq.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/seteqz.ll =================================================================== --- test/CodeGen/Mips/seteqz.ll +++ test/CodeGen/Mips/seteqz.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 0, align 4 @j = global i32 99, align 4 @@ -12,6 +13,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltiu ${{[0-9]+}}, 1 +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 %1 = load i32, i32* @j, align 4 %cmp1 = icmp eq i32 %1, 99 @@ -19,6 +21,7 @@ store i32 %conv2, i32* @r2, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setge.ll =================================================================== --- test/CodeGen/Mips/setge.ll +++ test/CodeGen/Mips/setge.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -17,6 +18,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32, i32* @m, align 4 Index: test/CodeGen/Mips/setgek.ll =================================================================== --- test/CodeGen/Mips/setgek.ll +++ test/CodeGen/Mips/setgek.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @k = global i32 10, align 4 @r1 = common global i32 0, align 4 @@ -12,6 +13,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slti ${{[0-9]+}}, -32768 +; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ; 16: xor ${{[0-9]+}}, ${{[0-9]+}} ret void Index: test/CodeGen/Mips/setle.ll =================================================================== --- test/CodeGen/Mips/setle.ll +++ test/CodeGen/Mips/setle.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32, i32* @m, align 4 Index: test/CodeGen/Mips/setlt.ll =================================================================== --- test/CodeGen/Mips/setlt.ll +++ test/CodeGen/Mips/setlt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setltk.ll =================================================================== --- test/CodeGen/Mips/setltk.ll +++ test/CodeGen/Mips/setltk.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -14,7 +15,8 @@ %cmp = icmp slt i32 %0, 10 %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 -; 16: slti $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $24 +; 16: slti $[[REGISTER:[0-9]+]], 10 +; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10 +; 16: move $[[REGISTER]], $24 ret void } Index: test/CodeGen/Mips/setne.ll =================================================================== --- test/CodeGen/Mips/setne.ll +++ test/CodeGen/Mips/setne.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, $[[REGISTER]] +; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setuge.ll =================================================================== --- test/CodeGen/Mips/setuge.ll +++ test/CodeGen/Mips/setuge.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32, i32* @m, align 4 Index: test/CodeGen/Mips/setugt.ll =================================================================== --- test/CodeGen/Mips/setugt.ll +++ test/CodeGen/Mips/setugt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setule.ll =================================================================== --- test/CodeGen/Mips/setule.ll +++ test/CodeGen/Mips/setule.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32, i32* @m, align 4 Index: test/CodeGen/Mips/setult.ll =================================================================== --- test/CodeGen/Mips/setult.ll +++ test/CodeGen/Mips/setult.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 @@ -16,6 +17,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setultk.ll =================================================================== --- test/CodeGen/Mips/setultk.ll +++ test/CodeGen/Mips/setultk.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 @@ -15,6 +16,7 @@ %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/slt.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/slt.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s + +define i32 @slt(i32 signext %a) nounwind readnone { + %1 = icmp slt i32 %a, 7 + ; CHECK-LABEL: slt: + ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4 + %2 = select i1 %1, i32 3, i32 4 + ret i32 %2 +} + +define i32 @sgt(i32 signext %a) { +entry: + ; CHECK-LABEL: sgt: + %cmp = icmp sgt i32 %a, 32767 + ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4 + %cond = select i1 %cmp, i32 7, i32 5 + ret i32 %cond +} Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -270,6 +270,10 @@ 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 +0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5 +0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256 +0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256 +0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x00 0x00 0x47 0x7c # CHECK: di Index: test/MC/Mips/micromips-el-fixup-data.s =================================================================== --- test/MC/Mips/micromips-el-fixup-data.s +++ test/MC/Mips/micromips-el-fixup-data.s @@ -16,7 +16,7 @@ addiu $sp, $sp, -16 bnez $9, lab1 -# CHECK: 09 b4 04 00 bne $9, $zero, 8 +# CHECK: 09 b4 04 00 bnez $9, 8 addu $zero, $zero, $zero lab1: Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -288,6 +288,10 @@ seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] + slt $3, $4, $5 # CHECK: slt $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x50] + slti $3, $4, 256 # CHECK: slti $3, $4, 256 # encoding: [0x90,0x64,0x01,0x00] + sltiu $3, $4, 256 # CHECK: sltiu $3, $4, 256 # encoding: [0xb0,0x64,0x01,0x00] + sltu $3, $4, $5 # CHECK: sltu $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x90] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]