Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -969,14 +969,18 @@ class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>; class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>; class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, - MMR6Arch<"addu16">; + MMR6Arch<"addu16"> { + int AddedComplexity = 1; +} class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, MMR6Arch<"and16">; class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, MMR6Arch<"andi16">; class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">; class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, - MMR6Arch<"or16">; + MMR6Arch<"or16"> { + int AddedComplexity = 1; +} class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -278,7 +278,6 @@ class MMArch { string Arch = "micromips"; - list Pattern = []; } class ADD_FM_MM op, bits<10> funct> : MMArch { Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -1002,6 +1002,11 @@ def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; +defm : SeteqPats; +defm : SetlePats; +defm : SetgtPats; +defm : SetgePats; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// @@ -1037,6 +1042,8 @@ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : MipsInstAlias<"slt $rs, $rt, $imm", + (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1639,11 +1639,11 @@ } def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; +let AdditionalPredicates = [NotInMicroMips] in { def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xa>; def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xb>; -let AdditionalPredicates = [NotInMicroMips] in { def ANDi : MMRel, StdMMR6Rel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, ADDI_FM<0xc>; @@ -1667,8 +1667,10 @@ ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; +let AdditionalPredicates = [NotInMicroMips] in { def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; +} let AdditionalPredicates = [NotInMicroMips] in { def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; @@ -2179,9 +2181,11 @@ (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; def : MipsInstAlias<"negu $rt, $rs", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; +let Predicates = [NotInMicroMips] in { def : MipsInstAlias< "slt $rs, $rt, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; +} def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; @@ -2563,10 +2567,12 @@ (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } +let AdditionalPredicates = [NotInMicroMips] in { defm : SeteqPats; defm : SetlePats; defm : SetgtPats; defm : SetgePats; +} defm : SetgeImmPats; // bswap pattern Index: test/CodeGen/Mips/brconlt.ll =================================================================== --- test/CodeGen/Mips/brconlt.ll +++ test/CodeGen/Mips/brconlt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 @@ -13,6 +14,7 @@ br i1 %cmp, label %if.end, label %if.then ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]] ; 16: $[[LABEL]]: Index: test/CodeGen/Mips/seteq.ll =================================================================== --- test/CodeGen/Mips/seteq.ll +++ test/CodeGen/Mips/seteq.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/setltk.ll =================================================================== --- test/CodeGen/Mips/setltk.ll +++ test/CodeGen/Mips/setltk.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -14,7 +15,8 @@ %cmp = icmp slt i32 %0, 10 %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 -; 16: slti $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $24 +; 16: slti $[[REGISTER:[0-9]+]], 10 +; MM32R6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10 +; 16: move $[[REGISTER]], $24 ret void } Index: test/CodeGen/Mips/setne.ll =================================================================== --- test/CodeGen/Mips/setne.ll +++ test/CodeGen/Mips/setne.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, $[[REGISTER]] +; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } Index: test/CodeGen/Mips/slt.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/slt.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s + +define i32 @slt(i32 signext %a) nounwind readnone { + %1 = icmp slt i32 %a, 7 + %2 = select i1 %1, i32 3, i32 4 + ret i32 %2 +} + +define i32 @sgt(i32 signext %a) { +entry: + %cmp = icmp sgt i32 %a, 32767 + %cond = select i1 %cmp, i32 7, i32 5 + ret i32 %cond +} + +; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -258,6 +258,10 @@ 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 +0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5 +0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256 +0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256 +0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x00 0x00 0x47 0x7c # CHECK: di Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -260,6 +260,10 @@ seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] + slt $3, $4, $5 # CHECK: slt $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x50] + slti $3, $4, 256 # CHECK: slti $3, $4, 256 # encoding: [0x90,0x64,0x01,0x00] + sltiu $3, $4, 256 # CHECK: sltiu $3, $4, 256 # encoding: [0xb0,0x64,0x01,0x00] + sltu $3, $4, $5 # CHECK: sltu $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x90] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]