Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1138,7 +1138,15 @@ (R0 == Mips::A0 && R1 == Mips::S6) || (R0 == Mips::A0 && R1 == Mips::A1) || (R0 == Mips::A0 && R1 == Mips::A2) || - (R0 == Mips::A0 && R1 == Mips::A3)) + (R0 == Mips::A0 && R1 == Mips::A3) || + (R0 == Mips::A1_64 && R1 == Mips::A2_64) || + (R0 == Mips::A1_64 && R1 == Mips::A3_64) || + (R0 == Mips::A2_64 && R1 == Mips::A3_64) || + (R0 == Mips::A0_64 && R1 == Mips::S5_64) || + (R0 == Mips::A0_64 && R1 == Mips::S6_64) || + (R0 == Mips::A0_64 && R1 == Mips::A1_64) || + (R0 == Mips::A0_64 && R1 == Mips::A2_64) || + (R0 == Mips::A0_64 && R1 == Mips::A3_64)) return true; return false; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -717,9 +717,15 @@ def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>, SRLV_FM_MM<0x90, 0>; def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>, - SRA_FM_MM<0xc0, 0>; + SRA_FM_MM<0xc0, 0> { + list Pattern = [(set GPR32Opnd:$rd, + (rotr GPR32Opnd:$rt, immZExt5:$shamt))]; + } def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, - SRLV_FM_MM<0xd0, 0>; + SRLV_FM_MM<0xd0, 0> { + list Pattern = [(set GPR32Opnd:$rd, + (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))]; + } /// Load and Store Instructions - aligned let DecoderMethod = "DecodeMemMMImm16" in { @@ -1055,4 +1061,7 @@ (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; def : MipsInstAlias<"srl $rd, $shamt", (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; +def : MipsInstAlias<"rotr $rt, $imm", + (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; +def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; } Index: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td @@ -757,7 +757,9 @@ def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; -def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; +} def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; @@ -791,9 +793,9 @@ let AdditionalPredicates = [NotInMicroMips] in { def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; } -def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; let AdditionalPredicates = [NotInMicroMips] in { Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1696,11 +1696,13 @@ } // Rotate Instructions -def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, - immZExt5>, - SRA_FM<2, 1>, ISA_MIPS32R2; -def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, - SRLV_FM<6, 1>, ISA_MIPS32R2; +let AdditionalPredicates = [NotInMicroMips] in { + def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, + immZExt5>, + SRA_FM<2, 1>, ISA_MIPS32R2; + def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, + SRLV_FM<6, 1>, ISA_MIPS32R2; +} /// Load and Store Instructions /// aligned @@ -2215,7 +2217,9 @@ (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"beqzl $rs,$offset", (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; -def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; +} def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; Index: llvm/trunk/test/CodeGen/Mips/rotate.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/rotate.ll +++ llvm/trunk/test/CodeGen/Mips/rotate.ll @@ -1,8 +1,15 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 ; CHECK: rotrv $2, $4 ; mips16: .ent rot0 +; MM32: li16 $2, 32 +; MM32: subu16 $2, $2, $5 +; MM32: rotrv $2, $4, $2 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { entry: %shl = shl i32 %a, %b @@ -14,6 +21,7 @@ ; CHECK: rotr $2, $4, 22 ; mips16: .ent rot1 +; MM32: rotr $2, $4, 22 define i32 @rot1(i32 %a) nounwind readnone { entry: %shl = shl i32 %a, 10 @@ -24,6 +32,7 @@ ; CHECK: rotrv $2, $4, $5 ; mips16: .ent rot2 +; MM32: rotrv $2, $4, $5 define i32 @rot2(i32 %a, i32 %b) nounwind readnone { entry: %shr = lshr i32 %a, %b @@ -35,6 +44,7 @@ ; CHECK: rotr $2, $4, 10 ; mips16: .ent rot3 +; MM32: rotr $2, $4, 10 define i32 @rot3(i32 %a) nounwind readnone { entry: %shr = lshr i32 %a, 10 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -189,3 +189,5 @@ 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) +0x00 0x00 0x7c 0x8b # CHECK: syscall +0x8c 0x01 0x7c 0x8b # CHECK: syscall 396 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -189,3 +189,5 @@ 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) +0x00 0x00 0x8b 0x7c # CHECK: syscall +0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -21,6 +21,7 @@ 0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17) +0x84 0x34 # CHECK: movep $5, $6, $2, $3 0x04 0xcc # CHECK: addu16 $6, $17, $4 0x44 0x21 # CHECK: and16 $16, $2 0x2e 0x56 # CHECK: andi16 $4, $5, 8 @@ -69,6 +70,15 @@ 0x00 0x01 0xf3 0x7c # CHECK: eretnc 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 +0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) +0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4) +0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27) +0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7 +0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7 +0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4) +0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4) +0x00 0x00 0x8b 0x7c # CHECK: syscall +0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4 0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -21,6 +21,16 @@ 0x45 0x2b # CHECK: jalr $9 0x45 0x23 # CHECK: jrc16 $9 0x44 0xb3 # CHECK: jrcaddiusp 20 +0x84 0x34 # CHECK: movep $5, $6, $2, $3 +0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) +0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4) +0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27) +0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7 +0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7 +0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4) +0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4) +0x00 0x00 0x8b 0x7c # CHECK: syscall +0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4 Index: llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s +++ llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s @@ -9,4 +9,5 @@ sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled Index: llvm/trunk/test/MC/Mips/micromips/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/invalid.s +++ llvm/trunk/test/MC/Mips/micromips/invalid.s @@ -39,7 +39,11 @@ pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset + rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -25,3 +25,6 @@ tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -172,3 +172,19 @@ she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand Index: llvm/trunk/test/MC/Mips/micromips32r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s @@ -65,6 +65,28 @@ lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] + ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] + lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] + lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] + lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] + lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40] + lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] + lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] + movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34] + rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0] + rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] + rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] + sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] + swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08] + swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08] + swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08] + swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40] + swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c] + syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58] modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8] mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] Index: llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s @@ -27,3 +27,6 @@ tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled Index: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s @@ -204,3 +204,19 @@ swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate + rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand Index: llvm/trunk/test/MC/Mips/micromips64r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s @@ -28,6 +28,28 @@ lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82] lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] + movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34] + ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] + lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] + lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] + lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] + lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40] + lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] + lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] + rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0] + rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] + rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] + sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] + swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08] + swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08] + swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08] + swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40] + swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c] + syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18] dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58] ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]