Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1849,9 +1849,15 @@
   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
   const TargetRegisterClass *DefinedRC =
       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
+
   if (!MO)
     MO = &MI->getOperand(OpIdx);
 
+  if (!DefinedRC) {
+    // This operand expects an immediate.
+    return !MO->isReg();
+  }
+
   if (isVALU(*MI) &&
       usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
 
@@ -1876,15 +1882,9 @@
     return isLegalRegOperand(MRI, OpInfo, *MO);
   }
 
-
   // Handle non-register types that are treated like immediates.
   assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
 
-  if (!DefinedRC) {
-    // This operand expects an immediate.
-    return true;
-  }
-
   return isImmOperandLegal(MI, OpIdx, *MO);
 }