Index: lib/Target/AMDGPU/R600ISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/R600ISelLowering.cpp
+++ lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -270,7 +270,6 @@
                      MI->getOperand(1).getImm());
     break;
   case AMDGPU::MOV_IMM_CONST_ADDR: {
-    //TODO: Perhaps combine this instruction with the next if possible
     auto MIB = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
                                  MI->getOperand(0).getReg(),
                                  AMDGPU::ALU_LITERAL_X);
@@ -2250,6 +2249,13 @@
     Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
     return true;
   }
+  case AMDGPU::MOV_IMM_CONST_ADDR:
+    // Check if the Imm slot is used. Taken from below.
+    if (cast<ConstantSDNode>(Imm)->getZExtValue())
+      return false;
+    Imm = Src.getOperand(0);
+    Src = DAG.getRegister(AMDGPU::ALU_LITERAL_X, MVT::i32);
+    return true;
   case AMDGPU::MOV_IMM_I32:
   case AMDGPU::MOV_IMM_F32: {
     unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
Index: test/CodeGen/AMDGPU/gv-const-addrspace.ll
===================================================================
--- test/CodeGen/AMDGPU/gv-const-addrspace.ll
+++ test/CodeGen/AMDGPU/gv-const-addrspace.ll
@@ -13,6 +13,7 @@
 
 ; EG: VTX_READ_32
 ; EG-NOT: MOVA_INT
+; EG-NOT: MOV
 
 define void @float(float addrspace(1)* %out, i32 %index) {
 entry:
@@ -30,6 +31,7 @@
 
 ; EG: VTX_READ_32
 ; EG-NOT: MOVA_INT
+; EG-NOT: MOV
 
 define void @i32(i32 addrspace(1)* %out, i32 %index) {
 entry:
@@ -49,6 +51,8 @@
 
 ; EG: VTX_READ_32
 ; EG-NOT: MOVA_INT
+; EG-NOT: MOV
+
 define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
   %gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
   %load = load i32, i32 addrspace(2)* %gep, align 4
@@ -66,6 +70,8 @@
 
 ; EG: VTX_READ_32
 ; EG-NOT: MOVA_INT
+; EG-NOT: MOV
+
 define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
   %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
   %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4