Index: llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
@@ -129,7 +129,7 @@
 enum AddressSpaces : unsigned {
   PRIVATE_ADDRESS  = 0, ///< Address space for private memory.
   GLOBAL_ADDRESS   = 1, ///< Address space for global memory (RAT0, VTX0).
-  CONSTANT_ADDRESS = 2, ///< Address space for constant memory
+  CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2)
   LOCAL_ADDRESS    = 3, ///< Address space for local memory.
   FLAT_ADDRESS     = 4, ///< Address space for flat memory.
   REGION_ADDRESS   = 5, ///< Address space for region memory.
Index: llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td
+++ llvm/trunk/lib/Target/AMDGPU/CaymanInstructions.td
@@ -206,6 +206,7 @@
   [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
 >;
 
+// 16-bit reads
 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
   [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
 >;
@@ -225,5 +226,30 @@
   [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
 >;
 
+// 8-bit reads
+def VTX_READ_CONSTANT_8_cm : VTX_READ_8_cm <2,
+  [(set i32:$dst_gpr, (az_extloadi8_constant ADDRVTX_READ:$src_gpr))]
+>;
+
+// 16-bit reads
+def VTX_READ_CONSTANT_16_cm : VTX_READ_16_cm <2,
+  [(set i32:$dst_gpr, (az_extloadi16_constant ADDRVTX_READ:$src_gpr))]
+>;
+
+// 32-bit reads
+def VTX_READ_CONSTANT_32_cm : VTX_READ_32_cm <2,
+  [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
+// 64-bit reads
+def VTX_READ_CONSTANT_64_cm : VTX_READ_64_cm <2,
+  [(set v2i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
+// 128-bit reads
+def VTX_READ_CONSTANT_128_cm : VTX_READ_128_cm <2,
+  [(set v4i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
 } // End isCayman
 
Index: llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td
+++ llvm/trunk/lib/Target/AMDGPU/EvergreenInstructions.td
@@ -239,6 +239,7 @@
   [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
 >;
 
+// 16-bit reads
 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
   [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
 >;
@@ -258,6 +259,31 @@
   [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
 >;
 
+// 8-bit reads
+def VTX_READ_CONSTANT_8_eg : VTX_READ_8_eg <2,
+  [(set i32:$dst_gpr, (az_extloadi8_constant ADDRVTX_READ:$src_gpr))]
+>;
+
+// 16-bit reads
+def VTX_READ_CONSTANT_16_eg : VTX_READ_16_eg <2,
+  [(set i32:$dst_gpr, (az_extloadi16_constant ADDRVTX_READ:$src_gpr))]
+>;
+
+// 32-bit reads
+def VTX_READ_CONSTANT_32_eg : VTX_READ_32_eg <2,
+  [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
+// 64-bit reads
+def VTX_READ_CONSTANT_64_eg : VTX_READ_64_eg <2,
+  [(set v2i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
+// 128-bit reads
+def VTX_READ_CONSTANT_128_eg : VTX_READ_128_eg <2,
+  [(set v4i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
+>;
+
 } // End Predicates = [isEG]
 
 //===----------------------------------------------------------------------===//