Index: lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetMachine.cpp
+++ lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -111,7 +111,7 @@
     EnableSSALoadStoreOpt("aarch64-ssa-load-store-opt",
                           cl::desc("Enable the load/store pair"
                                    " optimization pass in SSA form"),
-                          cl::init(false), cl::Hidden);
+                          cl::init(true), cl::Hidden);
 
 extern "C" void LLVMInitializeAArch64Target() {
   // Register the target.
Index: test/CodeGen/AArch64/ssa-ldst-opt.ll
===================================================================
--- test/CodeGen/AArch64/ssa-ldst-opt.ll
+++ test/CodeGen/AArch64/ssa-ldst-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=aarch64 -verify-machineinstrs -asm-verbose=false -aarch64-ssa-load-store-opt -o - %s | FileCheck %s
+; RUN: llc -march=aarch64 -verify-machineinstrs -asm-verbose=false -o - %s | FileCheck %s
 
 ; This test is for 'AArch64 load/store optimization in SSA form'.
 ; Find consecutive two 32-bit loads and consecutive two 32-bit stores that write the values of the consecutive 32-bit loads.