Index: lib/Transforms/Vectorize/LoopVectorize.cpp =================================================================== --- lib/Transforms/Vectorize/LoopVectorize.cpp +++ lib/Transforms/Vectorize/LoopVectorize.cpp @@ -4984,7 +4984,7 @@ continue; // FIXME: Currently we can't handle mixed accesses and predicated accesses if (IsPred) - return; + break; AccessList.push_back(&I); } Index: test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll =================================================================== --- /dev/null +++ test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll @@ -0,0 +1,52 @@ +; RUN: opt -S -loop-vectorize -instcombine -force-vector-width=2 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true -vectorize-num-stores-pred=1 -enable-cond-stores-vec < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-gnu" + +%pair = type { i64, i64 } + +; CHECK-LABEL: @load_gap_with_pred_store +; +; CHECK: min.iters.checked +; CHECK: %n.mod.vf = and i64 %[[N:.+]], 1 +; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 +; CHECK: %[[R:.+]] = select i1 %[[IsZero]], i64 2, i64 %n.mod.vf +; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; +; CHECK: vector.body: +; CHECK: %wide.vec = load <4 x i64>, <4 x i64>* %{{.*}} +; CHECK: %strided.vec = shufflevector <4 x i64> %wide.vec, <4 x i64> undef, <2 x i32> +; CHECK: %[[Result:.+]] = and <2 x i64> %strided.vec, %{{.*}} +; +; CHECK: pred.store.if +; CHECK: %[[X1:.+]] = extractelement <2 x i64> %[[Result]], i32 0 +; CHECK: store i64 %[[X1]], {{.*}} +; +; CHECK: pred.store.if +; CHECK: %[[X2:.+]] = extractelement <2 x i64> %[[Result]], i32 1 +; CHECK: store i64 %[[X2]], {{.*}} + +define void @load_gap_with_pred_store(%pair *%p, i64 %x, i64 %n) { +entry: + br label %for.body + +for.body: + %i = phi i64 [ %i.next, %if.merge ], [ 0, %entry ] + %f1 = getelementptr inbounds %pair, %pair* %p, i64 %i, i32 1 + %r0 = load i64, i64* %f1, align 8 + %r1 = and i64 %r0, %x + %r2 = icmp eq i64 %r1, %x + br i1 %r2, label %if.then, label %if.merge + +if.then: + store i64 %r1, i64* %f1, align 8 + br label %if.merge + +if.merge: + %i.next = add nuw nsw i64 %i, 1 + %cond = icmp slt i64 %i.next, %n + br i1 %cond, label %for.body, label %for.end + +for.end: + ret void +}