Index: lib/Support/Host.cpp =================================================================== --- lib/Support/Host.cpp +++ lib/Support/Host.cpp @@ -622,6 +622,7 @@ .Case("POWER7", "pwr7") .Case("POWER8", "pwr8") .Case("POWER8E", "pwr8") + .Case("POWER9", "pwr9") .Default(generic); } #elif defined(__linux__) && defined(__arm__) Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -47,6 +47,7 @@ def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; +def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">; def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; @@ -200,6 +201,8 @@ !listconcat(Power7FeatureList, Power8SpecificFeatures); list Power9SpecificFeatures = [FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0]; + list Power9FeatureList = + !listconcat(Power8FeatureList, Power9SpecificFeatures); } // Note: Future features to add when support is extended to more @@ -398,6 +401,8 @@ FeatureMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; +// FIXME: Same as P8 until the POWER9 scheduling info is available +def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>; def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, Index: lib/Target/PowerPC/PPCHazardRecognizers.cpp =================================================================== --- lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -162,8 +162,9 @@ unsigned Directive = DAG->MF.getSubtarget().getDarwinDirective(); // If we're using a special group-terminating nop, then we need only one. + // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 || - Directive == PPC::DIR_PWR8 ) + Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR9) return 1; return 5 - CurSlots; @@ -223,8 +224,10 @@ DAG->MF.getSubtarget().getDarwinDirective(); // If the group has now filled all of its slots, or if we're using a special // group-terminating nop, the group is complete. + // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 || - Directive == PPC::DIR_PWR8 || CurSlots == 6) { + Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR8 || + CurSlots == 6) { CurGroup.clear(); CurSlots = CurBranches = 0; } else { Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -921,6 +921,7 @@ case PPC::DIR_PWR6X: case PPC::DIR_PWR7: case PPC::DIR_PWR8: + case PPC::DIR_PWR9: setPrefFunctionAlignment(4); setPrefLoopAlignment(4); break; @@ -11175,7 +11176,8 @@ case PPC::DIR_PWR6: case PPC::DIR_PWR6X: case PPC::DIR_PWR7: - case PPC::DIR_PWR8: { + case PPC::DIR_PWR8: + case PPC::DIR_PWR9: { if (!ML) break; Index: lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.cpp +++ lib/Target/PowerPC/PPCInstrInfo.cpp @@ -93,6 +93,7 @@ unsigned Directive = DAG->MF.getSubtarget().getDarwinDirective(); + // FIXME: Leaving this as-is until we have POWER9 scheduling info if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) return new PPCDispatchGroupSBHazardRecognizer(II, DAG); @@ -181,6 +182,7 @@ case PPC::DIR_PWR6X: case PPC::DIR_PWR7: case PPC::DIR_PWR8: + // FIXME: Is this needed for POWER9? Latency += 2; break; } @@ -428,6 +430,8 @@ case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */ + // FIXME: Update when POWER9 scheduling model is ready. + case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; } DebugLoc DL; Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -56,6 +56,7 @@ DIR_PWR6X, DIR_PWR7, DIR_PWR8, + DIR_PWR9, DIR_64 }; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -170,6 +170,8 @@ case PPC::DIR_E5500: case PPC::DIR_PWR7: case PPC::DIR_PWR8: + // FIXME: Same as P8 until POWER9 scheduling info is available + case PPC::DIR_PWR9: return true; } } Index: lib/Target/PowerPC/PPCTargetTransformInfo.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -267,8 +267,9 @@ // For P7 and P8, floating-point instructions have a 6-cycle latency and // there are two execution units, so unroll by 12x for latency hiding. - if (Directive == PPC::DIR_PWR7 || - Directive == PPC::DIR_PWR8) + // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready + if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || + Directive == PPC::DIR_PWR9) return 12; // For most things, modern systems have two execution units (and