Index: llvm/trunk/include/llvm/Target/TargetSchedule.td
===================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td
@@ -76,8 +76,6 @@
 // See MCSchedule.h for detailed comments.
 class SchedMachineModel {
   int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
-  int MinLatency = -1; // Determines which instructions are allowed in a group.
-                       // (-1) inorder (0) ooo, (1): inorder +var latencies.
   int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
   int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
                                   // optimized loop dispatch/execution.
Index: llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
@@ -19,7 +19,6 @@
 def CortexA53Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
-  let MinLatency = 1 ;       // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 3;       // Optimistic load latency assuming bypass.
                              // This is overriden by OperandCycles if the
                              // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
@@ -19,7 +19,6 @@
 
 def ExynosM1Model : SchedMachineModel {
   let IssueWidth            =  4; // Up to 4 uops per cycle.
-  let MinLatency            =  0; // OoO.
   let MicroOpBufferSize     = 96; // ROB size.
   let LoopMicroOpBufferSize = 32; // Instruction queue size.
   let LoadLatency           =  4; // Optimistic load cases.
Index: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
@@ -1065,7 +1065,6 @@
 // Cortex-A8 machine model for scheduling and other instruction cost heuristics.
 def CortexA8Model : SchedMachineModel {
   let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 2; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/Lanai/LanaiSchedule.td
===================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiSchedule.td
+++ llvm/trunk/lib/Target/Lanai/LanaiSchedule.td
@@ -39,10 +39,6 @@
   // Max micro-ops that may be scheduled per cycle. [default = 1]
   let IssueWidth = 1;
 
-  // Determines which instructions are allowed in a group. 1 is an inorder
-  // CPU with variable latencies. [default = -1]
-  let MinLatency = 1;
-
   // Extra cycles for a mispredicted branch. [default = -1]
   let MispredictPenalty = 10;
 
Index: llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
@@ -597,7 +597,6 @@
 
 def PPC440Model : SchedMachineModel {
   let IssueWidth = 2;  // 2 instructions are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 5; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
@@ -160,7 +160,6 @@
 
 def PPCA2Model : SchedMachineModel {
   let IssueWidth = 1;  // 1 instruction is dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 6; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
@@ -311,7 +311,6 @@
 
 def PPCE500mcModel : SchedMachineModel {
   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 5; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
@@ -371,7 +371,6 @@
 
 def PPCE5500Model : SchedMachineModel {
   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 6; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
@@ -118,7 +118,6 @@
 
 def G5Model : SchedMachineModel {
   let IssueWidth = 4;  // 4 (non-branch) instructions are dispatched per cycle.
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
@@ -382,7 +382,6 @@
                        // branches), but the total internal issue bandwidth per
                        // cycle (from all queues) is 8.
 
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
@@ -391,7 +391,6 @@
                        // up to six non-branch instructions.
                        // up to two branches in a dispatch group.
 
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.