Index: include/llvm/Target/TargetLowering.h
===================================================================
--- include/llvm/Target/TargetLowering.h
+++ include/llvm/Target/TargetLowering.h
@@ -904,9 +904,9 @@
   /// given address space and alignment. If the access is allowed, the optional
   /// final parameter returns if the access is also fast (as defined by the
   /// target).
-  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
-                          unsigned AddrSpace = 0, unsigned Alignment = 1,
-                          bool *Fast = nullptr) const;
+  virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
+                                  unsigned AddrSpace = 0, unsigned Alignment = 1,
+                                  bool *Fast = nullptr) const;
 
   /// Returns the target specific optimal type for load and store operations as
   /// a result of memset, memcpy, and memmove lowering.
Index: lib/Target/AMDGPU/SIISelLowering.h
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.h
+++ lib/Target/AMDGPU/SIISelLowering.h
@@ -143,6 +143,10 @@
                                StringRef Constraint, MVT VT) const override;
   ConstraintType getConstraintType(StringRef Constraint) const override;
   SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;
+
+  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
+    unsigned AddrSpace = 0, unsigned Alignment = 1,
+    bool *Fast = nullptr) const override;
 };
 
 } // End namespace llvm
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2119,6 +2119,19 @@
 // Custom DAG optimizations
 //===----------------------------------------------------------------------===//
 
+bool SITargetLowering::allowsMemoryAccess(LLVMContext &Context,
+                                          const DataLayout &DL, EVT VT,
+                                          unsigned AddrSpace,
+                                          unsigned Alignment,
+                                          bool *Fast) const {
+
+  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS && VT.getStoreSize() > 4)
+    return false;
+
+  return AMDGPUTargetLowering::allowsMemoryAccess(Context, DL, VT, AddrSpace,
+                                                  Alignment, Fast);
+}
+
 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
                                                      DAGCombinerInfo &DCI) const {
   EVT VT = N->getValueType(0);