Index: Sparc.td =================================================================== --- Sparc.td +++ Sparc.td @@ -35,6 +35,9 @@ def FeatureVIS3 : SubtargetFeature<"vis3", "IsVIS3", "true", "Enable Visual Instruction Set extensions III">; +def FeatureLeon + : SubtargetFeature<"leon", "IsLeon", "true", + "Enable LEON extensions">; def FeatureHardQuad : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", @@ -49,6 +52,7 @@ include "SparcRegisterInfo.td" include "SparcCallingConv.td" +include "SparcSchedule.td" include "SparcInstrInfo.td" def SparcInstrInfo : InstrInfo; @@ -90,6 +94,43 @@ def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3]>; +// LEON 2 FT generic +def : Processor<"leon2", LEON2Itineraries, + [FeatureLeon]>; + +// LEON 2 FT (AT697E) +// TO DO: Place-holder: Processor specific features will be added *very* soon here. +def : Processor<"at697e", LEON2Itineraries, + [FeatureLeon]>; + +// LEON 2 FT (AT697F) +// TO DO: Place-holder: Processor specific features will be added *very* soon here. +def : Processor<"at697f", LEON2Itineraries, + [FeatureLeon]>; + + +// LEON 3 FT generic +def : Processor<"leon3", LEON3Itineraries, + [FeatureLeon]>; + +// LEON 3 FT (UT699) +// TO DO: Place-holder: Processor specific features will be added *very* soon here. +def : Processor<"ut699", LEON3Itineraries, + [FeatureLeon]>; + +// LEON3 FT (GR712RC) +// TO DO: Place-holder: Processor specific features will be added *very* soon here. +def : Processor<"gr712rc", LEON3Itineraries, + [FeatureLeon]>; + +// LEON 4 FT generic +def : Processor<"leon4", LEON4Itineraries, + [FeatureLeon]>; + +// LEON 4 FT (GR740) +// TO DO: Place-holder: Processor specific features will be added *very* soon here. +def : Processor<"gr740", LEON4Itineraries, + [FeatureLeon]> {} //===----------------------------------------------------------------------===// // Declare the target which we are implementing Index: SparcInstrFormats.td =================================================================== --- SparcInstrFormats.td +++ SparcInstrFormats.td @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// -class InstSP pattern> - : Instruction { +class InstSP pattern, + InstrItinClass itin = NoItinerary> + : Instruction { field bits<32> Inst; let Namespace = "SP"; @@ -24,6 +25,8 @@ let DecoderNamespace = "Sparc"; field bits<32> SoftFail = 0; + + let Itinerary = itin; } //===----------------------------------------------------------------------===// @@ -31,8 +34,9 @@ //===----------------------------------------------------------------------===// // Format 2 instructions -class F2 pattern> - : InstSP { +class F2 pattern, + InstrItinClass itin = NoItinerary> + : InstSP { bits<3> op2; bits<22> imm22; let op = 0; // op = 0 @@ -42,8 +46,9 @@ // Specific F2 classes: SparcV8 manual, page 44 // -class F2_1 op2Val, dag outs, dag ins, string asmstr, list pattern> - : F2 { +class F2_1 op2Val, dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F2 { bits<5> rd; let op2 = op2Val; @@ -52,7 +57,8 @@ } class F2_2 op2Val, bit annul, dag outs, dag ins, string asmstr, - list pattern> : F2 { + list pattern, InstrItinClass itin = NoItinerary> + : F2 { bits<4> cond; let op2 = op2Val; @@ -61,8 +67,9 @@ } class F2_3 op2Val, bit annul, bit pred, - dag outs, dag ins, string asmstr, list pattern> - : InstSP { + dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : InstSP { bits<2> cc; bits<4> cond; bits<19> imm19; @@ -77,9 +84,9 @@ let Inst{18-0} = imm19; } -class F2_4 cond, bit annul, bit pred, - dag outs, dag ins, string asmstr, list pattern> - : InstSP { +class F2_4 cond, bit annul, bit pred, dag outs, dag ins, + string asmstr, list pattern, InstrItinClass itin = NoItinerary> + : InstSP { bits<16> imm16; bits<5> rs1; @@ -100,8 +107,9 @@ // Format #3 instruction classes in the Sparc //===----------------------------------------------------------------------===// -class F3 pattern> - : InstSP { +class F3 pattern, + InstrItinClass itin = NoItinerary> + : InstSP { bits<5> rd; bits<6> op3; bits<5> rs1; @@ -114,7 +122,8 @@ // Specific F3 classes: SparcV8 manual, page 44 // class F3_1_asi opVal, bits<6> op3val, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = NoItinerary> + : F3 { bits<8> asi; bits<5> rs2; @@ -127,13 +136,14 @@ } class F3_1 opVal, bits<6> op3val, dag outs, dag ins, string asmstr, - list pattern> : F3_1_asi { + list pattern, InstrItinClass itin = IIC_iu_instr> + : F3_1_asi { let asi = 0; } class F3_2 opVal, bits<6> op3val, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = IIC_iu_instr> + : F3 { bits<13> simm13; let op = opVal; @@ -145,7 +155,8 @@ // floating-point class F3_3 opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = NoItinerary> + : F3 { bits<5> rs2; let op = opVal; @@ -157,7 +168,8 @@ // floating-point unary operations. class F3_3u opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = NoItinerary> + : F3 { bits<5> rs2; let op = opVal; @@ -170,7 +182,8 @@ // floating-point compares. class F3_3c opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = NoItinerary> + : F3 { bits<5> rs2; let op = opVal; @@ -182,7 +195,8 @@ // Shift by register rs2. class F3_Sr opVal, bits<6> op3val, bit xVal, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = IIC_iu_instr> + : F3 { bit x = xVal; // 1 for 64-bit shifts. bits<5> rs2; @@ -196,7 +210,8 @@ // Shift by immediate. class F3_Si opVal, bits<6> op3val, bit xVal, dag outs, dag ins, - string asmstr, list pattern> : F3 { + string asmstr, list pattern, InstrItinClass itin = IIC_iu_instr> + : F3 { bit x = xVal; // 1 for 64-bit shifts. bits<6> shcnt; // shcnt32 / shcnt64. @@ -210,17 +225,21 @@ // Define rr and ri shift instructions with patterns. multiclass F3_S Op3Val, bit XVal, SDNode OpNode, - ValueType VT, RegisterClass RC> { + ValueType VT, RegisterClass RC, + InstrItinClass itin = IIC_iu_instr> { def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), !strconcat(OpcStr, " $rs1, $rs2, $rd"), - [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; + [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], + itin>; def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), !strconcat(OpcStr, " $rs1, $shcnt, $rd"), - [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; + [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], + itin>; } -class F4 op3, dag outs, dag ins, string asmstr, list pattern> - : InstSP { +class F4 op3, dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : InstSP { bits<5> rd; let op = 2; @@ -230,9 +249,9 @@ class F4_1 op3, dag outs, dag ins, - string asmstr, list pattern> - : F4 { - + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F4 { bit intcc; bits<2> cc; bits<4> cond; @@ -243,12 +262,12 @@ let Inst{13} = 0; let Inst{17-14} = cond; let Inst{18} = intcc; - } class F4_2 op3, dag outs, dag ins, - string asmstr, list pattern> - : F4 { + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F4 { bit intcc; bits<2> cc; bits<4> cond; @@ -262,8 +281,9 @@ } class F4_3 op3, bits<6> opf_low, dag outs, dag ins, - string asmstr, list pattern> - : F4 { + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F4 { bits<4> cond; bit intcc; bits<2> opf_cc; @@ -278,8 +298,9 @@ } class F4_4r op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, - string asmstr, list pattern> - : F4 { + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F4 { bits <5> rs1; bits <5> rs2; let Inst{18-14} = rs1; @@ -291,8 +312,9 @@ class F4_4i op3, bits<3> rcond, dag outs, dag ins, - string asmstr, list pattern> - : F4 { + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F4 { bits<5> rs1; bits<10> simm10; let Inst{18-14} = rs1; @@ -302,9 +324,10 @@ } -class TRAPSP op3Val, bit isimm, dag outs, dag ins, string asmstr, - list pattern>: F3 { - +class TRAPSP op3Val, bit isimm, dag outs, dag ins, + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : F3 { bits<4> cond; bits<2> cc; @@ -317,15 +340,20 @@ } -class TRAPSPrr op3Val, dag outs, dag ins, string asmstr, - list pattern>: TRAPSP { +class TRAPSPrr op3Val, dag outs, dag ins, + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : TRAPSP { bits<5> rs2; let Inst{10-5} = 0; let Inst{4-0} = rs2; } -class TRAPSPri op3Val, dag outs, dag ins, string asmstr, - list pattern>: TRAPSP { + +class TRAPSPri op3Val, dag outs, dag ins, + string asmstr, list pattern, + InstrItinClass itin = NoItinerary> + : TRAPSP { bits<8> imm; let Inst{10-8} = 0; Index: SparcInstrInfo.td =================================================================== --- SparcInstrInfo.td +++ SparcInstrInfo.td @@ -264,53 +264,61 @@ /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. multiclass F3_12 Op3Val, SDNode OpNode, - RegisterClass RC, ValueType Ty, Operand immOp> { + RegisterClass RC, ValueType Ty, Operand immOp, + InstrItinClass itin = IIC_iu_instr> { def rr : F3_1<2, Op3Val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2), !strconcat(OpcStr, " $rs1, $rs2, $rd"), - [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>; + [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], + itin>; def ri : F3_2<2, Op3Val, (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), !strconcat(OpcStr, " $rs1, $simm13, $rd"), - [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>; + [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], + itin>; } /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no /// pattern. -multiclass F3_12np Op3Val> { +multiclass F3_12np Op3Val, InstrItinClass itin = IIC_iu_instr> { def rr : F3_1<2, Op3Val, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), - !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; + !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], + itin>; def ri : F3_2<2, Op3Val, (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), - !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>; + !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], + itin>; } // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Load Op3Val, SDPatternOperator OpNode, - RegisterClass RC, ValueType Ty> { + RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> { def rr : F3_1<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr), !strconcat(OpcStr, " [$addr], $dst"), - [(set Ty:$dst, (OpNode ADDRrr:$addr))]>; + [(set Ty:$dst, (OpNode ADDRrr:$addr))], + itin>; def ri : F3_2<3, Op3Val, (outs RC:$dst), (ins MEMri:$addr), !strconcat(OpcStr, " [$addr], $dst"), - [(set Ty:$dst, (OpNode ADDRri:$addr))]>; + [(set Ty:$dst, (OpNode ADDRri:$addr))], + itin>; } // TODO: Instructions of the LoadASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. class LoadASI Op3Val, SDPatternOperator OpNode, - RegisterClass RC, ValueType Ty> : + RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> : F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), !strconcat(OpcStr, "a [$addr] $asi, $dst"), []>; // LoadA multiclass - As above, but also define alternate address space variant multiclass LoadA Op3Val, bits<6> LoadAOp3Val, - SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : - Load { + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, + InstrItinClass itin = NoItinerary> : + Load { def Arr : LoadASI; } @@ -318,38 +326,43 @@ // It is unlikely that general-purpose code could make use of it. // CAS is preferred for sparc v9. def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), - "ldstub [$addr], $dst", []>; + "ldstub [$addr], $dst", []>; def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), - "ldstub [$addr], $dst", []>; + "ldstub [$addr], $dst", []>; def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi), "ldstuba [$addr] $asi, $dst", []>; // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store Op3Val, SDPatternOperator OpNode, - RegisterClass RC, ValueType Ty> { + RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { def rr : F3_1<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd), !strconcat(OpcStr, " $rd, [$addr]"), - [(OpNode Ty:$rd, ADDRrr:$addr)]>; + [(OpNode Ty:$rd, ADDRrr:$addr)], + itin>; def ri : F3_2<3, Op3Val, (outs), (ins MEMri:$addr, RC:$rd), !strconcat(OpcStr, " $rd, [$addr]"), - [(OpNode Ty:$rd, ADDRri:$addr)]>; + [(OpNode Ty:$rd, ADDRri:$addr)], + itin>; } // TODO: Instructions of the StoreASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. class StoreASI Op3Val, - SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, + InstrItinClass itin = IIC_st> : F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), - !strconcat(OpcStr, "a $rd, [$addr] $asi"), - []>; + !strconcat(OpcStr, "a $rd, [$addr] $asi"), + [], + itin>; multiclass StoreA Op3Val, bits<6> StoreAOp3Val, - SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, + InstrItinClass itin = IIC_st> : Store { - def Arr : StoreASI; + def Arr : StoreASI; } //===----------------------------------------------------------------------===// @@ -444,16 +457,16 @@ } let DecoderMethod = "DecodeLoadIntPair" in - defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32>; + defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>; // Section B.2 - Load Floating-point Instructions, p. 92 let DecoderMethod = "DecodeLoadFP" in { - defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; - def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>, + defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; + def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>, Requires<[HasV9]>; } let DecoderMethod = "DecodeLoadDFP" in { - defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; + defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>; def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, Requires<[HasV9]>; } @@ -464,7 +477,7 @@ let DecoderMethod = "DecodeLoadCP" in defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>; let DecoderMethod = "DecodeLoadCPPair" in - defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32>; + defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>; let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { let rd = 0 in { @@ -479,9 +492,9 @@ let Defs = [FSR] in { let rd = 0 in { def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), - "ld [$addr], %fsr", []>; + "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), - "ld [$addr], %fsr", []>; + "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; } let rd = 1 in { def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), @@ -499,7 +512,7 @@ } let DecoderMethod = "DecodeStoreIntPair" in - defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>; + defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>; // Section B.5 - Store Floating-point Instructions, p. 97 let DecoderMethod = "DecodeStoreFP" in { @@ -508,7 +521,7 @@ Requires<[HasV9]>; } let DecoderMethod = "DecodeStoreDFP" in { - defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; + defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>; def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, Requires<[HasV9]>; } @@ -520,20 +533,20 @@ defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; let DecoderMethod = "DecodeStoreCPPair" in - defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32>; + defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; let DecoderMethod = "DecodeStoreCP", rd = 0 in { let Defs = [CPSR] in { def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), - "st %csr, [$addr]", []>; + "st %csr, [$addr]", [], IIC_st>; def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins), - "st %csr, [$addr]", []>; + "st %csr, [$addr]", [], IIC_st>; } let Defs = [CPQ] in { def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins), - "std %cq, [$addr]", []>; + "std %cq, [$addr]", [], IIC_std>; def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins), - "std %cq, [$addr]", []>; + "std %cq, [$addr]", [], IIC_std>; } } @@ -541,15 +554,15 @@ let rd = 0 in { let Defs = [FSR] in { def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), - "st %fsr, [$addr]", []>; + "st %fsr, [$addr]", [], IIC_st>; def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), - "st %fsr, [$addr]", []>; + "st %fsr, [$addr]", [], IIC_st>; } let Defs = [FQ] in { def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins), - "std %fq, [$addr]", []>; + "std %fq, [$addr]", [], IIC_std>; def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins), - "std %fq, [$addr]", []>; + "std %fq, [$addr]", [], IIC_std>; } } let rd = 1, Defs = [FSR] in { @@ -582,7 +595,8 @@ def SETHIi: F2_1<0b100, (outs IntRegs:$rd), (ins i32imm:$imm22), "sethi $imm22, $rd", - [(set i32:$rd, SETHIimm:$imm22)]>; + [(set i32:$rd, SETHIimm:$imm22)], + IIC_iu_instr>; // Section B.10 - NOP Instruction, p. 105 // (It's a special case of SETHI) @@ -677,13 +691,13 @@ // Section B.18 - Multiply Instructions, p. 113 let Defs = [Y] in { - defm UMUL : F3_12np<"umul", 0b001010>; - defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>; + defm UMUL : F3_12np<"umul", 0b001010, IIC_iu_umul>; + defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>; } let Defs = [Y, ICC] in { - defm UMULCC : F3_12np<"umulcc", 0b011010>; - defm SMULCC : F3_12np<"smulcc", 0b011011>; + defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>; + defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>; } let Defs = [Y, ICC], Uses = [Y, ICC] in { @@ -692,13 +706,13 @@ // Section B.19 - Divide Instructions, p. 115 let Uses = [Y], Defs = [Y] in { - defm UDIV : F3_12np<"udiv", 0b001110>; - defm SDIV : F3_12np<"sdiv", 0b001111>; + defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>; + defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>; } let Uses = [Y], Defs = [Y, ICC] in { - defm UDIVCC : F3_12np<"udivcc", 0b011110>; - defm SDIVCC : F3_12np<"sdivcc", 0b011111>; + defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>; + defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>; } // Section B.20 - SAVE and RESTORE, p. 117 @@ -724,26 +738,30 @@ // conditional branch class: class BranchSP pattern> - : F2_2<0b010, 0, (outs), ins, asmstr, pattern>; + : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>; // conditional branch with annul class: class BranchSPA pattern> - : F2_2<0b010, 1, (outs), ins, asmstr, pattern>; + : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>; // Conditional branch class on %icc|%xcc with predication: multiclass IPredBranch CCPattern> { def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), - !strconcat("b$cond ", !strconcat(regstr, ", $imm19")), - CCPattern>; + !strconcat("b$cond ", !strconcat(regstr, ", $imm19")), + CCPattern, + IIC_iu_instr>; def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), - !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), - []>; + !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), + [], + IIC_iu_instr>; def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")), - []>; + [], + IIC_iu_instr>; def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")), - []>; + [], + IIC_iu_instr>; } } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 @@ -779,26 +797,26 @@ // floating-point conditional branch class: class FPBranchSP pattern> - : F2_2<0b110, 0, (outs), ins, asmstr, pattern>; + : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; // floating-point conditional branch with annul class: class FPBranchSPA pattern> - : F2_2<0b110, 1, (outs), ins, asmstr, pattern>; + : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; // Conditional branch class on %fcc0-%fcc3 with predication: multiclass FPredBranch { def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, FCCRegs:$cc), - "fb$cond $cc, $imm19", []>; + "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>; def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, FCCRegs:$cc), - "fb$cond,a $cc, $imm19", []>; + "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>; def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, FCCRegs:$cc), - "fb$cond,pn $cc, $imm19", []>; + "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>; def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, FCCRegs:$cc), - "fb$cond,a,pn $cc, $imm19", []>; + "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>; } } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 @@ -837,7 +855,9 @@ let Uses = [O6], hasDelaySlot = 1, isCall = 1 in { def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), - "call $disp", []> { + "call $disp", + [], + IIC_jmp_or_call> { bits<30> disp; let op = 1; let Inst{29-0} = disp; @@ -848,11 +868,13 @@ def CALLrr : F3_1<2, 0b111000, (outs), (ins MEMrr:$ptr, variable_ops), "call $ptr", - [(call ADDRrr:$ptr)]>; + [(call ADDRrr:$ptr)], + IIC_jmp_or_call>; def CALLri : F3_2<2, 0b111000, (outs), (ins MEMri:$ptr, variable_ops), "call $ptr", - [(call ADDRri:$ptr)]>; + [(call ADDRri:$ptr)], + IIC_jmp_or_call>; } } @@ -861,10 +883,16 @@ // JMPL Instruction. let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, DecoderMethod = "DecodeJMPL" in { - def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr), - "jmpl $addr, $dst", []>; - def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr), - "jmpl $addr, $dst", []>; + def JMPLrr: F3_1<2, 0b111000, + (outs IntRegs:$dst), (ins MEMrr:$addr), + "jmpl $addr, $dst", + [], + IIC_jmp_or_call>; + def JMPLri: F3_2<2, 0b111000, + (outs IntRegs:$dst), (ins MEMri:$addr), + "jmpl $addr, $dst", + [], + IIC_jmp_or_call>; } // Section A.3 - Synthetic Instructions, p. 85 @@ -872,21 +900,33 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, isCodeGenOnly = 1 in { let rd = 0, rs1 = 15 in - def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), - "jmp %o7+$val", [(retflag simm13:$val)]>; + def RETL: F3_2<2, 0b111000, + (outs), (ins i32imm:$val), + "jmp %o7+$val", + [(retflag simm13:$val)], + IIC_jmp_or_call>; let rd = 0, rs1 = 31 in - def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), - "jmp %i7+$val", []>; + def RET: F3_2<2, 0b111000, + (outs), (ins i32imm:$val), + "jmp %i7+$val", + [], + IIC_jmp_or_call>; } // Section B.26 - Return from Trap Instruction let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { - def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr), - "rett $addr", []>; - def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr), - "rett $addr", []>; + def RETTrr : F3_1<2, 0b111001, + (outs), (ins MEMrr:$addr), + "rett $addr", + [], + IIC_jmp_or_call>; + def RETTri : F3_2<2, 0b111001, + (outs), (ins MEMri:$addr), + "rett $addr", + [], + IIC_jmp_or_call>; } @@ -894,21 +934,25 @@ // conditional branch class: let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in { - def TRAPrr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, - CCOp:$cond), - "t$cond $rs1 + $rs2", []>; - def TRAPri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm, - CCOp:$cond), - "t$cond $rs1 + $imm", []>; + def TRAPrr : TRAPSPrr<0b111010, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), + "t$cond $rs1 + $rs2", + []>; + def TRAPri : TRAPSPri<0b111010, + (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), + "t$cond $rs1 + $imm", + []>; } multiclass TRAP { - def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, - CCOp:$cond), - !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>; - def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm, - CCOp:$cond), - !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>; + def rr : TRAPSPrr<0b111010, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), + !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), + []>; + def ri : TRAPSPri<0b111010, + (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), + !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), + []>; } let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in @@ -1010,11 +1054,13 @@ def FITOS : F3_3u<2, 0b110100, 0b011000100, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fitos $rs2, $rd", - [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>; + [(set FPRegs:$rd, (SPitof FPRegs:$rs2))], + IIC_fpu_fast_instr>; def FITOD : F3_3u<2, 0b110100, 0b011001000, (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fitod $rs2, $rd", - [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>; + [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))], + IIC_fpu_fast_instr>; def FITOQ : F3_3u<2, 0b110100, 0b011001100, (outs QFPRegs:$rd), (ins FPRegs:$rs2), "fitoq $rs2, $rd", @@ -1025,11 +1071,13 @@ def FSTOI : F3_3u<2, 0b110100, 0b011010001, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fstoi $rs2, $rd", - [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>; + [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))], + IIC_fpu_fast_instr>; def FDTOI : F3_3u<2, 0b110100, 0b011010010, (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fdtoi $rs2, $rd", - [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>; + [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))], + IIC_fpu_fast_instr>; def FQTOI : F3_3u<2, 0b110100, 0b011010011, (outs FPRegs:$rd), (ins QFPRegs:$rs2), "fqtoi $rs2, $rd", @@ -1040,7 +1088,8 @@ def FSTOD : F3_3u<2, 0b110100, 0b011001001, (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fstod $rs2, $rd", - [(set f64:$rd, (fextend f32:$rs2))]>; + [(set f64:$rd, (fextend f32:$rs2))], + IIC_fpu_stod>; def FSTOQ : F3_3u<2, 0b110100, 0b011001101, (outs QFPRegs:$rd), (ins FPRegs:$rs2), "fstoq $rs2, $rd", @@ -1049,7 +1098,8 @@ def FDTOS : F3_3u<2, 0b110100, 0b011000110, (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fdtos $rs2, $rd", - [(set f32:$rd, (fround f64:$rs2))]>; + [(set f32:$rd, (fround f64:$rs2))], + IIC_fpu_fast_instr>; def FDTOQ : F3_3u<2, 0b110100, 0b011001110, (outs QFPRegs:$rd), (ins DFPRegs:$rs2), "fdtoq $rs2, $rd", @@ -1073,22 +1123,26 @@ def FNEGS : F3_3u<2, 0b110100, 0b000000101, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fnegs $rs2, $rd", - [(set f32:$rd, (fneg f32:$rs2))]>; + [(set f32:$rd, (fneg f32:$rs2))], + IIC_fpu_negs>; def FABSS : F3_3u<2, 0b110100, 0b000001001, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fabss $rs2, $rd", - [(set f32:$rd, (fabs f32:$rs2))]>; + [(set f32:$rd, (fabs f32:$rs2))], + IIC_fpu_abs>; // Floating-point Square Root Instructions, p.145 def FSQRTS : F3_3u<2, 0b110100, 0b000101001, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fsqrts $rs2, $rd", - [(set f32:$rd, (fsqrt f32:$rs2))]>; + [(set f32:$rd, (fsqrt f32:$rs2))], + IIC_fpu_sqrts>; def FSQRTD : F3_3u<2, 0b110100, 0b000101010, (outs DFPRegs:$rd), (ins DFPRegs:$rs2), "fsqrtd $rs2, $rd", - [(set f64:$rd, (fsqrt f64:$rs2))]>; + [(set f64:$rd, (fsqrt f64:$rs2))], + IIC_fpu_sqrtd>; def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, (outs QFPRegs:$rd), (ins QFPRegs:$rs2), "fsqrtq $rs2, $rd", @@ -1101,11 +1155,13 @@ def FADDS : F3_3<2, 0b110100, 0b001000001, (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fadds $rs1, $rs2, $rd", - [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>; + [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))], + IIC_fpu_fast_instr>; def FADDD : F3_3<2, 0b110100, 0b001000010, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "faddd $rs1, $rs2, $rd", - [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>; + [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))], + IIC_fpu_fast_instr>; def FADDQ : F3_3<2, 0b110100, 0b001000011, (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), "faddq $rs1, $rs2, $rd", @@ -1115,11 +1171,13 @@ def FSUBS : F3_3<2, 0b110100, 0b001000101, (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fsubs $rs1, $rs2, $rd", - [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>; + [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))], + IIC_fpu_fast_instr>; def FSUBD : F3_3<2, 0b110100, 0b001000110, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fsubd $rs1, $rs2, $rd", - [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>; + [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))], + IIC_fpu_fast_instr>; def FSUBQ : F3_3<2, 0b110100, 0b001000111, (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), "fsubq $rs1, $rs2, $rd", @@ -1131,11 +1189,13 @@ def FMULS : F3_3<2, 0b110100, 0b001001001, (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fmuls $rs1, $rs2, $rd", - [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>; + [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))], + IIC_fpu_muls>; def FMULD : F3_3<2, 0b110100, 0b001001010, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fmuld $rs1, $rs2, $rd", - [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>; + [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))], + IIC_fpu_muld>; def FMULQ : F3_3<2, 0b110100, 0b001001011, (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), "fmulq $rs1, $rs2, $rd", @@ -1146,7 +1206,8 @@ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fsmuld $rs1, $rs2, $rd", [(set f64:$rd, (fmul (fextend f32:$rs1), - (fextend f32:$rs2)))]>; + (fextend f32:$rs2)))], + IIC_fpu_muld>; def FDMULQ : F3_3<2, 0b110100, 0b001101110, (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fdmulq $rs1, $rs2, $rd", @@ -1157,11 +1218,13 @@ def FDIVS : F3_3<2, 0b110100, 0b001001101, (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fdivs $rs1, $rs2, $rd", - [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>; + [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))], + IIC_fpu_divs>; def FDIVD : F3_3<2, 0b110100, 0b001001110, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fdivd $rs1, $rs2, $rd", - [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>; + [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))], + IIC_fpu_divd>; def FDIVQ : F3_3<2, 0b110100, 0b001001111, (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), "fdivq $rs1, $rs2, $rd", @@ -1179,11 +1242,13 @@ def FCMPS : F3_3c<2, 0b110101, 0b001010001, (outs), (ins FPRegs:$rs1, FPRegs:$rs2), "fcmps $rs1, $rs2", - [(SPcmpfcc f32:$rs1, f32:$rs2)]>; + [(SPcmpfcc f32:$rs1, f32:$rs2)], + IIC_fpu_fast_instr>; def FCMPD : F3_3c<2, 0b110101, 0b001010010, (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fcmpd $rs1, $rs2", - [(SPcmpfcc f64:$rs1, f64:$rs2)]>; + [(SPcmpfcc f64:$rs1, f64:$rs2)], + IIC_fpu_fast_instr>; def FCMPQ : F3_3c<2, 0b110101, 0b001010011, (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), "fcmpq $rs1, $rs2", @@ -1213,7 +1278,8 @@ def TLS_CALL : InstSP<(outs), (ins calltarget:$disp, TLSSym:$sym, variable_ops), "call $disp, $sym", - [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { + [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)], + IIC_jmp_or_call> { bits<30> disp; let op = 1; let Inst{29-0} = disp; Index: SparcSchedule.td =================================================================== --- SparcSchedule.td +++ SparcSchedule.td @@ -0,0 +1,121 @@ +//===-- SparcSchedule.td - Describe the Sparc Itineries ----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +def IIC_iu_or_fpu_instr : InstrItinClass; +def IIC_iu_instr : InstrItinClass; +def IIC_fpu_normal_instr : InstrItinClass; +def IIC_fpu_fast_instr : InstrItinClass; +def IIC_jmp_or_call : InstrItinClass; +def IIC_ldd : InstrItinClass; +def IIC_st : InstrItinClass; +def IIC_std : InstrItinClass; +def IIC_iu_smul : InstrItinClass; +def IIC_iu_umul : InstrItinClass; +def IIC_iu_div : InstrItinClass; +def IIC_ticc : InstrItinClass; +def IIC_ldstub : InstrItinClass; +def IIC_fpu_muls : InstrItinClass; +def IIC_fpu_muld : InstrItinClass; +def IIC_fpu_divs : InstrItinClass; +def IIC_fpu_divd : InstrItinClass; +def IIC_fpu_sqrts : InstrItinClass; +def IIC_fpu_sqrtd : InstrItinClass; +def IIC_fpu_abs : InstrItinClass; +def IIC_fpu_movs : InstrItinClass; +def IIC_fpu_negs : InstrItinClass; +def IIC_fpu_stod : InstrItinClass; + +def LEONIU : FuncUnit; // integer unit +def LEONFPU : FuncUnit; // floating-point unit + +// Ref: http://www.atmel.com/Images/doc4226.pdf + +def LEON2Itineraries : ProcessorItineraries< +[LEONIU, LEONFPU], [], [ + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [7, 1]>, + InstrItinData], [7, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [5, 1]>, + InstrItinData], [5, 1]>, + InstrItinData], [35, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [16, 1]>, + InstrItinData], [21, 1]>, + InstrItinData], [20, 1]>, + InstrItinData], [36, 1]>, + InstrItinData], [37, 1]>, + InstrItinData], [65, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]> +]>; + +def LEON3Itineraries : ProcessorItineraries< +[LEONIU, LEONFPU], [], [ + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [7, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [5, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [35, 1]>, + InstrItinData], [5, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [16, 1]>, + InstrItinData], [17, 1]>, + InstrItinData], [24, 1]>, + InstrItinData], [25, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [4, 1]> +]>; + +def LEON4Itineraries : ProcessorItineraries< +[LEONIU, LEONFPU], [], [ + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [7, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [1, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [35, 1]>, + InstrItinData], [5, 1]>, + InstrItinData], [3, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [4, 1]>, + InstrItinData], [16, 1]>, + InstrItinData], [17, 1]>, + InstrItinData], [24, 1]>, + InstrItinData], [25, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [2, 1]>, + InstrItinData], [4, 1]> +]>; Index: SparcSubtarget.h =================================================================== --- SparcSubtarget.h +++ SparcSubtarget.h @@ -32,6 +32,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo { virtual void anchor(); bool IsV9; + bool IsLeon; bool V8DeprecatedInsts; bool IsVIS, IsVIS2, IsVIS3; bool Is64Bit; @@ -63,6 +64,7 @@ bool enableMachineScheduler() const override; bool isV9() const { return IsV9; } + bool isLeon() const { return IsLeon; } bool isVIS() const { return IsVIS; } bool isVIS2() const { return IsVIS2; } bool isVIS3() const { return IsVIS3; }