Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10085,7 +10085,8 @@
   // value.
   // TODO: Handle store large -> read small portion.
   // TODO: Handle TRUNCSTORE/LOADEXT
-  if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
+  if (OptLevel != CodeGenOpt::None &&
+      ISD::isNormalLoad(N) && !LD->isVolatile()) {
     if (ISD::isNON_TRUNCStore(Chain.getNode())) {
       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
       if (PrevST->getBasePtr() == Ptr &&
Index: test/CodeGen/ARM/alloc-no-stack-realign.ll
===================================================================
--- test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -21,8 +21,9 @@
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
+; NO-REALIGN: mov	r[[R3:[0-9]+]], r[[R1]]
+; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]!
+; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]
 
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
Index: test/CodeGen/ARM/dag-combine-ldst.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/dag-combine-ldst.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -O0 | FileCheck %s -check-prefix=CHECK_O0
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -O1 | FileCheck %s -check-prefix=CHECK_O1
+
+; In /O0, the addition must not be eliminated. This happens when the load
+; and store are folded by the DAGCombiner. In /O1 and above, the optimization
+; must be executed.
+
+; CHECK_O0: add	r0, r0, #2
+; CHECK_O1-NOT: add	r0, r0, #2
+
+define i32 @main() {
+bb:
+  %tmp = alloca i32, align 4
+  %tmp1 = alloca i32, align 4
+  store i32 0, i32* %tmp, align 4
+  store i32 0, i32* %tmp1, align 4
+  %tmp2 = load i32, i32* %tmp1, align 4
+  %tmp3 = add nsw i32 %tmp2, 2
+  store i32 %tmp3, i32* %tmp1, align 4
+  %tmp4 = load i32, i32* %tmp1, align 4
+  %tmp5 = icmp eq i32 %tmp4, 2
+  br i1 %tmp5, label %bb6, label %bb7
+
+bb6:                                              ; preds = %bb
+  store i32 0, i32* %tmp, align 4
+  br label %bb8
+
+bb7:                                              ; preds = %bb
+  store i32 5, i32* %tmp, align 4
+  br label %bb8
+
+bb8:                                              ; preds = %bb7, %bb6
+  %tmp9 = load i32, i32* %tmp, align 4
+  ret i32 %tmp9
+}
Index: test/CodeGen/SystemZ/swift-return.ll
===================================================================
--- test/CodeGen/SystemZ/swift-return.ll
+++ test/CodeGen/SystemZ/swift-return.ll
@@ -49,10 +49,9 @@
 ; CHECK: a %r2, 172(%r15)
 ; CHECK: a %r2, 176(%r15)
 ; CHECK-O0-LABEL: test2:
-; CHECK-O0: la %[[REG1:r[0-9]+]], 168(%r15)
 ; CHECK-O0: st %r2, [[SPILL1:[0-9]+]](%r15)
-; CHECK-O0: lgr %r2, %[[REG1]]
 ; CHECK-O0: l %r3, [[SPILL1]](%r15)
+; CHECK-O0: la %r2, 168(%r15)
 ; CHECK-O0: brasl %r14, gen2
 ; CHECK-O0-DAG: l %r{{.*}}, 184(%r15)
 ; CHECK-O0-DAG: l %r{{.*}}, 180(%r15)