Index: lib/Target/AMDGPU/SIRegisterInfo.h =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.h +++ lib/Target/AMDGPU/SIRegisterInfo.h @@ -59,6 +59,8 @@ unsigned FIOperandNum, RegScavenger *RS) const override; + std::string getRegAsmName(unsigned Reg) const override; + unsigned getHWRegIndex(unsigned Reg) const override; /// \brief Return the 'base' register class for this register. Index: lib/Target/AMDGPU/SIRegisterInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.cpp +++ lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "SIRegisterInfo.h" +#include "InstPrinter/AMDGPUInstPrinter.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -501,6 +502,11 @@ } } +std::string SIRegisterInfo::getRegAsmName(unsigned Reg) const { + return StringRef(AMDGPUInstPrinter::getRegisterName(Reg)); +} + + unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const { return getEncodingValue(Reg) & 0xff; } Index: lib/Target/AMDGPU/SIRegisterInfo.td =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.td +++ lib/Target/AMDGPU/SIRegisterInfo.td @@ -81,7 +81,7 @@ multiclass FLAT_SCR_LOHI_m ci_e, bits<16> vi_e> { def _ci : SIReg; def _vi : SIReg; - def "" : SIReg<"", 0>; + def "" : SIReg; } class FlatReg encoding> : @@ -101,12 +101,12 @@ // SGPR registers foreach Index = 0-103 in { - def SGPR#Index : SIReg <"SGPR"#Index, Index>; + def SGPR#Index : SIReg <"s"#Index, Index>; } // VGPR registers foreach Index = 0-255 in { - def VGPR#Index : SIReg <"VGPR"#Index, Index> { + def VGPR#Index : SIReg <"v"#Index, Index> { let HWEncoding{8} = 1; } } Index: test/CodeGen/AMDGPU/flat-scratch-reg.ll =================================================================== --- test/CodeGen/AMDGPU/flat-scratch-reg.ll +++ test/CodeGen/AMDGPU/flat-scratch-reg.ll @@ -7,7 +7,7 @@ ; XNACK: ; NumSgprs: 12 define void @no_vcc_no_flat() { entry: - call void asm sideeffect "", "~{SGPR7}"() + call void asm sideeffect "", "~{s7}"() ret void } @@ -16,7 +16,7 @@ ; XNACK: ; NumSgprs: 12 define void @vcc_no_flat() { entry: - call void asm sideeffect "", "~{SGPR7},~{VCC}"() + call void asm sideeffect "", "~{s7},~{vcc}"() ret void } @@ -25,7 +25,7 @@ ; VI: ; NumSgprs: 14 define void @no_vcc_flat() { entry: - call void asm sideeffect "", "~{SGPR7},~{FLAT_SCR}"() + call void asm sideeffect "", "~{s7},~{flat_scratch}"() ret void } @@ -34,6 +34,6 @@ ; VI: ; NumSgprs: 14 define void @vcc_flat() { entry: - call void asm sideeffect "", "~{SGPR7},~{VCC},~{FLAT_SCR}"() + call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"() ret void } Index: test/CodeGen/AMDGPU/inline-reg-constraints.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/inline-reg-constraints.ll @@ -0,0 +1,128 @@ +; RUN: llc < %s -march=amdgcn -mcpu=kaveri -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=CI --check-prefix=NO-XNACK +; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI --check-prefix=NO-XNACK +; RUN: llc < %s -march=amdgcn -mcpu=kaveri -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=CI --check-prefix=NO-XNACK-CI +; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI --check-prefix=NO-XNACK-VI +; RUN: llc < %s -march=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI --check-prefix=XNACK + +; GCN-LABEL: {{^}}test1: +; NO-XNACK: ; NumSgprs: 1 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 5 +; XNACK: ; NumVgprs: 1 +define void @test1() { +entry: + call void asm sideeffect "", ""() + ret void +} + +; GCN-LABEL: {{^}}test2: +; NO-XNACK: ; NumSgprs: 8 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 12 +; XNACK: ; NumVgprs: 1 +define void @test2() { +entry: + call void asm sideeffect "", "~{s7}"() + ret void +} + +; GCN-LABEL: {{^}}test3: +; NO-XNACK: ; NumSgprs: 102 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 106 +; XNACK: ; NumVgprs: 1 +define void @test3() { +entry: + call void asm sideeffect "", "~{s12},~{s101}"() + ret void +} + +; GCN-LABEL: {{^}}test4: +; NO-XNACK: ; NumSgprs: 1 +; NO-XNACK: ; NumVgprs: 4 +; XNACK: ; NumSgprs: 5 +; XNACK: ; NumVgprs: 4 +define void @test4() { +entry: + call void asm sideeffect "", "~{v3}"() + ret void +} + +; GCN-LABEL: {{^}}test5: +; NO-XNACK: ; NumSgprs: 2 +; NO-XNACK: ; NumVgprs: 256 +; XNACK: ; NumSgprs: 6 +; XNACK: ; NumVgprs: 256 +define void @test5() { +entry: + call void asm sideeffect "", "~{v255},~{s1}"() + ret void +} + +; GCN-LABEL: {{^}}test6: +; NO-XNACK: ; NumSgprs: 102 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 106 +; XNACK: ; NumVgprs: 1 +define void @test6() { +entry: + call void asm sideeffect "", "~{s12},~{s101}"() + ret void +} + +; GCN-LABEL: {{^}}test7: +; NO-XNACK: ; NumSgprs: 3 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 5 +; XNACK: ; NumVgprs: 1 +define void @test7() { +entry: + call void asm sideeffect "", "~{vcc},~{vcc_lo}"() + ret void +} + +; GCN-LABEL: {{^}}test8: +; NO-XNACK: ; NumSgprs: 128 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 132 +; XNACK: ; NumVgprs: 1 +define void @test8() { +entry: + call void asm sideeffect "", "~{exec},~{exec_hi}"() + ret void +} + +; GCN-LABEL: {{^}}test9: +; NO-XNACK-CI: ; NumSgprs: 5 +; NO-XNACK-VI: ; NumSgprs: 7 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 7 +; XNACK: ; NumVgprs: 1 +define void @test9() { +entry: + call void asm sideeffect "", "~{flat_scratch_lo}"() + ret void +} + +; GCN-LABEL: {{^}}test10: +; NO-XNACK-CI: ; NumSgprs: 5 +; NO-XNACK-VI: ; NumSgprs: 7 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 7 +; XNACK: ; NumVgprs: 1 +define void @test10() { +entry: + call void asm sideeffect "", "~{flat_scratch}"() + ret void +} + +; GCN-LABEL: {{^}}test11: +; NO-XNACK: ; NumSgprs: 1 +; NO-XNACK: ; NumVgprs: 1 +; XNACK: ; NumSgprs: 5 +; XNACK: ; NumVgprs: 1 +define void @test11() { +entry: + call void asm sideeffect "", "~{scc},~{m0}"() + ret void +} Index: test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll =================================================================== --- test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll +++ test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll @@ -15,9 +15,9 @@ ; mark 128-bit SGPR registers as used so they are unavailable for the ; scratch resource descriptor - call void asm sideeffect "", "~{SGPR4},~{SGPR8},~{SGPR12},~{SGPR16},~{SGPR20},~{SGPR24},~{SGPR28}" () - call void asm sideeffect "", "~{SGPR32},~{SGPR36},~{SGPR40},~{SGPR44},~{SGPR48},~{SGPR52},~{SGPR56}" () - call void asm sideeffect "", "~{SGPR60},~{SGPR64},~{SGPR68}" () + call void asm sideeffect "", "~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28}" () + call void asm sideeffect "", "~{s32},~{s36},~{s40},~{s44},~{s48},~{s52},~{s56}" () + call void asm sideeffect "", "~{s60},~{s64},~{s68}" () ret void } Index: test/CodeGen/AMDGPU/spill-scavenge-offset.ll =================================================================== --- test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -20,13 +20,13 @@ %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr ; mark most VGPR registers as used to increase register pressure - call void asm sideeffect "", "~{VGPR4},~{VGPR8},~{VGPR12},~{VGPR16},~{VGPR20},~{VGPR24},~{VGPR28},~{VGPR32}" () - call void asm sideeffect "", "~{VGPR36},~{VGPR40},~{VGPR44},~{VGPR48},~{VGPR52},~{VGPR56},~{VGPR60},~{VGPR64}" () - call void asm sideeffect "", "~{VGPR68},~{VGPR72},~{VGPR76},~{VGPR80},~{VGPR84},~{VGPR88},~{VGPR92},~{VGPR96}" () - call void asm sideeffect "", "~{VGPR100},~{VGPR104},~{VGPR108},~{VGPR112},~{VGPR116},~{VGPR120},~{VGPR124},~{VGPR128}" () - call void asm sideeffect "", "~{VGPR132},~{VGPR136},~{VGPR140},~{VGPR144},~{VGPR148},~{VGPR152},~{VGPR156},~{VGPR160}" () - call void asm sideeffect "", "~{VGPR164},~{VGPR168},~{VGPR172},~{VGPR176},~{VGPR180},~{VGPR184},~{VGPR188},~{VGPR192}" () - call void asm sideeffect "", "~{VGPR196},~{VGPR200},~{VGPR204},~{VGPR208},~{VGPR212},~{VGPR216},~{VGPR220},~{VGPR224}" () + call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" () + call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" () + call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" () + call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" () + call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" () + call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" () + call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" () %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr