Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h
+++ lib/Target/ARM/ARMISelLowering.h
@@ -336,6 +336,8 @@
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  StringRef Constraint, MVT VT) const override;
 
+    const char *LowerXConstraint(EVT ConstraintVT) const override;
+
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     /// true it means one of the asm constraint of the inline asm instruction
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -11494,6 +11494,19 @@
   return false;
 }
 
+const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const {
+  if (!Subtarget->hasVFP2())
+    return "r";
+  if (ConstraintVT.isFloatingPoint())
+    return "w";
+  if (ConstraintVT.isVector() && Subtarget->hasNEON() &&
+     (ConstraintVT.getSizeInBits() == 64 ||
+      ConstraintVT.getSizeInBits() == 128))
+    return "w";
+
+  return "r";
+}
+
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 ARMTargetLowering::ConstraintType
Index: test/CodeGen/ARM/inlineasm-X-allocation.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/inlineasm-X-allocation.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfpv2 %s -o - | FileCheck %s  -check-prefix=novfp
+; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefix=vfp
+
+; vfp-LABEL: f1
+; vfp-CHECK: vadd.f32 s0, s0, s0
+
+; In the novfp case, the compiler is forced to assign a core register.
+; The register are not available in this case, but the compiler
+; behaved as expected.
+
+; novfp-LABEL: f1
+; novfp-CHECK: vadd.f32 r0, r0, r0
+
+define arm_aapcs_vfpcc void @f1(float %f) {
+entry:
+  call void asm sideeffect "vadd.f32 $0, $0, $0", "X" (float %f) nounwind
+  ret void
+}
Index: test/CodeGen/ARM/inlineasm-X-constraint.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/inlineasm-X-constraint.ll
@@ -0,0 +1,94 @@
+; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -o - | FileCheck %s
+
+; CHECK-LABEL: f1
+; CHECK: vmsr fpscr
+; CHECK: vadd.f64
+define arm_aapcs_vfpcc double @f1(double %f, i32 %pscr_value) {
+entry:
+  %f.addr = alloca double, align 8
+  store double %f, double* %f.addr, align 8
+  call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwind
+  %0 = load double, double* %f.addr, align 8
+  %add = fadd double %0, %0
+  ret double %add
+}
+
+; CHECK-LABEL: f2
+; CHECK: vmsr fpscr
+; CHECK: mul
+define arm_aapcs_vfpcc i32 @f2(i32 %f, i32 %pscr_value) {
+entry:
+  %f.addr = alloca i32, align 4
+  store i32 %f, i32* %f.addr, align 4
+  call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
+  %0 = load i32, i32* %f.addr, align 4
+  %mul = mul i32 %0, %0
+  ret i32 %mul
+}
+
+; CHECK-LABEL: f3
+; CHECK: vmsr fpscr
+; CHECK: vmul.i8
+define arm_aapcs_vfpcc <8 x i8> @f3() {
+entry:
+  %vector_res_int8x8 = alloca <8 x i8>, align 8
+  %0 = getelementptr inbounds <8 x i8>, <8 x i8>* %vector_res_int8x8, i32 0, i32 0
+  call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(<8 x i8>* nonnull %vector_res_int8x8, i32 undef) nounwind
+  %1 = load <8 x i8>, <8 x i8>* %vector_res_int8x8, align 8
+  %mul = mul <8 x i8> %1, %1
+  ret <8 x i8> %mul
+}
+
+; We can emit integer constants.
+; CHECK-LABEL: f4
+; CHECK: add r0, r0, #2
+define void @f4() {
+entry:
+  tail call void asm sideeffect "add r0, r0, $0", "X"(i32 2)
+  ret void
+}
+
+; We can emit function labels.
+; CHECK-LABEL: f5
+; CHECK: bl f4
+define void @f5() {
+entry:
+  tail call void asm sideeffect "bl $0", "X"(void ()* nonnull @f4)
+  ret void
+}
+
+; CHECK-LABEL: f6
+; CHECK: bl foo
+
+; We should be able to get the address of f4. However we can't see through
+; the bitcast and we end up emitting a register.
+; CHECK: bl r
+
+declare void @foo(...)
+
+define void @f6() nounwind {
+entry:
+  tail call void asm sideeffect "bl $0", "X"(void (...)* @foo) nounwind
+  tail call void asm sideeffect "bl $0", "X"(void (...)* bitcast (void ()* @f4 to void (...)*)) nounwind
+  ret void
+}
+
+; Ideally this would give the block address of bb, but this requires us to see
+; through blockaddress.
+
+; CHECK-LABEL: f7
+; CHECK: bl
+define void @f7() {
+  call void asm sideeffect "bl $0", "X"( i8* blockaddress(@f7, %bb) )
+  br label %bb
+bb:
+  ret void
+}
+
+; CHECK-LABEL: f8
+; CHECK: str	r{{.*}}, [r0]
+define void @f8(i32 *%x) {
+entry:
+  tail call void asm sideeffect "add $0, r0, r0", "=*X"(i32 *%x)
+  ret void
+}