Page MenuHomePhabricator

AMDGPU/SI: Fix spilling of 96-bit registers
ClosedPublic

Authored by tstellarAMD on Apr 12 2016, 10:18 AM.

Details

Summary

It seems like this was broken in r252327. I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.

Diff Detail

Repository
rL LLVM

Event Timeline

tstellarAMD retitled this revision from to AMDGPU/SI: Fix spilling of 96-bit registers.
tstellarAMD updated this object.
tstellarAMD added a reviewer: arsenm.
tstellarAMD added a subscriber: llvm-commits.
arsenm accepted this revision.Apr 12 2016, 10:26 AM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Apr 12 2016, 10:26 AM
nhaehnle accepted this revision.Apr 12 2016, 10:26 AM
nhaehnle added a reviewer: nhaehnle.
nhaehnle added a subscriber: nhaehnle.

LGTM

This revision was automatically updated to reflect the committed changes.