Index: include/llvm/MC/MCRegisterInfo.h
===================================================================
--- include/llvm/MC/MCRegisterInfo.h
+++ include/llvm/MC/MCRegisterInfo.h
@@ -104,6 +104,7 @@
 ///
 struct MCRegisterDesc {
   uint32_t Name;      // Printable name for the reg (for debugging)
+  uint32_t AsmName;   // Assembly name for the reg
   uint32_t SubRegs;   // Sub-register set, described above
   uint32_t SuperRegs; // Super-register set, described above
 
@@ -164,6 +165,7 @@
   const unsigned *RegUnitMaskSequences;       // Pointer to lane mask sequences
                                               // for register units.
   const char *RegStrings;                     // Pointer to the string table.
+  const char *RegAsmStrings;                  // Pointer to the asm names table.
   const char *RegClassStrings;                // Pointer to the class strings.
   const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
                                               // array.
@@ -250,6 +252,7 @@
                           const MCPhysReg *DL,
                           const unsigned *RUMS,
                           const char *Strings,
+                          const char *AsmStrings,
                           const char *ClassStrings,
                           const uint16_t *SubIndices,
                           unsigned NumIndices,
@@ -263,6 +266,7 @@
     DiffLists = DL;
     RegUnitMaskSequences = RUMS;
     RegStrings = Strings;
+    RegAsmStrings = AsmStrings;
     RegClassStrings = ClassStrings;
     NumClasses = NC;
     RegUnitRoots = RURoots;
@@ -368,6 +372,12 @@
     return RegStrings + get(RegNo).Name;
   }
 
+  /// \brief Return the target-specific assembly name for the specified physical
+  /// register.
+  const char *getAsmName(unsigned RegNo) const {
+    return RegAsmStrings + get(RegNo).AsmName;
+  }
+
   /// \brief Return the number of registers this target has (useful for
   /// sizing arrays holding per register information)
   unsigned getNumRegs() const {
Index: utils/TableGen/CodeGenRegisters.h
===================================================================
--- utils/TableGen/CodeGenRegisters.h
+++ utils/TableGen/CodeGenRegisters.h
@@ -139,6 +139,8 @@
 
     const std::string &getName() const;
 
+    std::string getAsmName() const;
+
     // Extract more information from TheDef. This is used to build an object
     // graph after all CodeGenRegister objects have been created.
     void buildObjectGraph(CodeGenRegBank&);
Index: utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- utils/TableGen/CodeGenRegisters.cpp
+++ utils/TableGen/CodeGenRegisters.cpp
@@ -150,6 +150,11 @@
   return TheDef->getName();
 }
 
+std::string CodeGenRegister::getAsmName() const {
+  assert(TheDef && "no def");
+  return TheDef->getValueAsString("AsmName");
+}
+
 namespace {
 // Iterate over all register units in a set of registers.
 class RegUnitIterator {
Index: utils/TableGen/RegisterInfoEmitter.cpp
===================================================================
--- utils/TableGen/RegisterInfoEmitter.cpp
+++ utils/TableGen/RegisterInfoEmitter.cpp
@@ -812,12 +812,14 @@
   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
 
   SequenceToOffsetTable<std::string> RegStrings;
+  SequenceToOffsetTable<std::string> RegAsmStrings;
 
   // Precompute register lists for the SequenceToOffsetTable.
   unsigned i = 0;
   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
     const auto &Reg = *I;
     RegStrings.add(Reg.getName());
+    RegAsmStrings.add(Reg.getAsmName());
 
     // Compute the ordered sub-register list.
     SetVector<const CodeGenRegister*> SR;
@@ -916,14 +918,22 @@
   RegStrings.emit(OS, printChar);
   OS << "};\n\n";
 
+  // Emit the asm names table.
+  RegAsmStrings.layout();
+  OS << "extern const char " << TargetName << "RegAsmStrings[] = {\n";
+  RegAsmStrings.emit(OS, printChar);
+  OS << "};\n\n";
+
   OS << "extern const MCRegisterDesc " << TargetName
      << "RegDesc[] = { // Descriptors\n";
-  OS << "  { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
+  OS << "  { " << RegStrings.get("") << ", " << RegAsmStrings.get("")
+     << ", 0, 0, 0, 0, 0 },\n";
 
   // Emit the register descriptors now.
   i = 0;
   for (const auto &Reg : Regs) {
     OS << "  { " << RegStrings.get(Reg.getName()) << ", "
+       << RegAsmStrings.get(Reg.getAsmName()) << ", "
        << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
        << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
        << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", "
@@ -1042,7 +1052,8 @@
      << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
      << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
-     << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
+     << TargetName << "RegAsmStrings, " << TargetName << "RegClassStrings, "
+     << TargetName << "SubRegIdxLists, "
      << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
      << TargetName << "SubRegIdxRanges, " << TargetName
      << "RegEncodingTable);\n\n";
@@ -1380,6 +1391,7 @@
   OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
   OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n";
   OS << "extern const char " << TargetName << "RegStrings[];\n";
+  OS << "extern const char " << TargetName << "RegAsmStrings[];\n";
   OS << "extern const char " << TargetName << "RegClassStrings[];\n";
   OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
   OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
@@ -1404,6 +1416,7 @@
      << "                     " << TargetName << "RegDiffLists,\n"
      << "                     " << TargetName << "LaneMaskLists,\n"
      << "                     " << TargetName << "RegStrings,\n"
+     << "                     " << TargetName << "RegAsmStrings,\n"
      << "                     " << TargetName << "RegClassStrings,\n"
      << "                     " << TargetName << "SubRegIdxLists,\n"
      << "                     " << SubRegIndicesSize + 1 << ",\n"