TargetRegisterInfo: Add getAsmName() to MCRegisterInfo.

[SamWot]

Summary

This method returns assembly name for register derived from TableGen field AsmName. getAsmName() uses generated table with assembly names. This table nad method works similar to TargetRegStrings table and MCRegisterInfo::getName().
This is needed to allow TargetLowering::getRegForInlineAsmConstraint() to use assembly names to match register constraints. Currently TargetLowering::getRegForInlineAsmConstraint() uses names of register definition in .td file.
Also watch this revision: http://reviews.llvm.org/D15614

[• tstellarAMD]

utils/TableGen/RegisterInfoEmitter.cpp

921–925

I think there may be concerns about increasing the binary size with this new table. Aren't we emitting the same table in GenXXXAsmWriter.inc? If so, could we modify the asm writer to use this new table instead?

[MatzeB]

Some targets have a gigantic number of registers (AMDGPU has ~3500 register and I am aware of an out of tree target with >10000 registers). I'd prefer a solution which does not increase the size of MCRegisterDesc at the very least we should find a way to share the name table with the AsmWriter code.

[SamWot]

Thanks Tom and Matthias,
I didn't actually find InstPrinter::getRegisterName(). Looks like it is possible to simply use it for inline assembly and no changes in core LLVM are required.
I will close this review.

include/llvm/MC/MCRegisterInfo.h

 /// register.  The SubRegs field is a zero terminated array of registers that
 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
 /// of AX. The SuperRegs field is a zero terminated array of registers that are
 /// super-registers of the specific register, e.g. RAX, EAX, are
 /// super-registers of AX.
 ///
 struct MCRegisterDesc {
   uint32_t Name;      // Printable name for the reg (for debugging)
+  uint32_t AsmName;   // Assembly name for the reg
   uint32_t SubRegs;   // Sub-register set, described above
   uint32_t SuperRegs; // Super-register set, described above
 
   // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
   // sub-register in SubRegs.
   uint32_t SubRegIndices;
 
   // RegUnits - Points to the list of register units. The low 4 bits holds the
private:
   const MCRegisterClass *Classes;             // Pointer to the regclass array
   unsigned NumClasses;                        // Number of entries in the array
   unsigned NumRegUnits;                       // Number of regunits.
   const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
   const MCPhysReg *DiffLists;                 // Pointer to the difflists array
   const unsigned *RegUnitMaskSequences;       // Pointer to lane mask sequences
                                               // for register units.
   const char *RegStrings;                     // Pointer to the string table.
+  const char *RegAsmStrings;                  // Pointer to the asm names table.
   const char *RegClassStrings;                // Pointer to the class strings.
   const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
                                               // array.
   const SubRegCoveredBits *SubRegIdxRanges;   // Pointer to the subreg covered
                                               // bit ranges array.
   unsigned NumSubRegIndices;                  // Number of subreg indices.
   const uint16_t *RegEncodingTable;           // Pointer to array of register
                                               // encodings.
public:
   void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
                           unsigned PC,
                           const MCRegisterClass *C, unsigned NC,
                           const MCPhysReg (*RURoots)[2],
                           unsigned NRU,
                           const MCPhysReg *DL,
                           const unsigned *RUMS,
                           const char *Strings,
+                          const char *AsmStrings,
                           const char *ClassStrings,
                           const uint16_t *SubIndices,
                           unsigned NumIndices,
                           const SubRegCoveredBits *SubIdxRanges,
                           const uint16_t *RET) {
     Desc = D;
     NumRegs = NR;
     RAReg = RA;
     PCReg = PC;
     Classes = C;
     DiffLists = DL;
     RegUnitMaskSequences = RUMS;
     RegStrings = Strings;
+    RegAsmStrings = AsmStrings;
     RegClassStrings = ClassStrings;
     NumClasses = NC;
     RegUnitRoots = RURoots;
     NumRegUnits = NRU;
     SubRegIndices = SubIndices;
     NumSubRegIndices = NumIndices;
     SubRegIdxRanges = SubIdxRanges;
     RegEncodingTable = RET;
public:
   unsigned getSubRegIdxOffset(unsigned Idx) const;
 
   /// \brief Return the human-readable symbolic target-specific name for the
   /// specified physical register.
   const char *getName(unsigned RegNo) const {
     return RegStrings + get(RegNo).Name;
   }
 
+  /// \brief Return the target-specific assembly name for the specified physical
+  /// register.
+  const char *getAsmName(unsigned RegNo) const {
+    return RegAsmStrings + get(RegNo).AsmName;
+  }
+
   /// \brief Return the number of registers this target has (useful for
   /// sizing arrays holding per register information)
   unsigned getNumRegs() const {
     return NumRegs;
   }
 
   /// \brief Return the number of sub-register indices
   /// understood by the target. Index 0 is reserved for the no-op sub-register,

utils/TableGen/CodeGenRegisters.h

struct CodeGenRegister {
     // Map SubRegIndex -> Register.
     typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
         SubRegMap;
 
     CodeGenRegister(Record *R, unsigned Enum);
 
     const std::string &getName() const;
 
+    std::string getAsmName() const;
+
     // Extract more information from TheDef. This is used to build an object
     // graph after all CodeGenRegister objects have been created.
     void buildObjectGraph(CodeGenRegBank&);
 
     // Lazily compute a map of all sub-registers.
     // This includes unique entries for all sub-sub-registers.
     const SubRegMap &computeSubRegs(CodeGenRegBank&);
 

utils/TableGen/CodeGenRegisters.cpp

void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
   }
 }
 
 const std::string &CodeGenRegister::getName() const {
   assert(TheDef && "no def");
   return TheDef->getName();
 }
 
+std::string CodeGenRegister::getAsmName() const {
+  assert(TheDef && "no def");
+  return TheDef->getValueAsString("AsmName");
+}
+
 namespace {
 // Iterate over all register units in a set of registers.
 class RegUnitIterator {
   CodeGenRegister::Vec::const_iterator RegI, RegE;
   CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
 
 public:
   RegUnitIterator(const CodeGenRegister::Vec &Regs):

utils/TableGen/RegisterInfoEmitter.cpp

RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
 
   // Keep track of sub-register names as well. These are not differentially
   // encoded.
   typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
   SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
 
   SequenceToOffsetTable<std::string> RegStrings;
+  SequenceToOffsetTable<std::string> RegAsmStrings;
 
   // Precompute register lists for the SequenceToOffsetTable.
   unsigned i = 0;
   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
     const auto &Reg = *I;
     RegStrings.add(Reg.getName());
+    RegAsmStrings.add(Reg.getAsmName());
 
     // Compute the ordered sub-register list.
     SetVector<const CodeGenRegister*> SR;
     Reg.addSubRegsPreOrder(SR, RegBank);
     diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
     DiffSeqs.add(SubRegLists[i]);
 
     // Compute the corresponding sub-register indexes.
#endif
   OS << "};\n\n";
 
   // Emit the string table.
   RegStrings.layout();
   OS << "extern const char " << TargetName << "RegStrings[] = {\n";
   RegStrings.emit(OS, printChar);
   OS << "};\n\n";
 
+  // Emit the asm names table.
+  RegAsmStrings.layout();
+  OS << "extern const char " << TargetName << "RegAsmStrings[] = {\n";
+  RegAsmStrings.emit(OS, printChar);
+  OS << "};\n\n";
+
   OS << "extern const MCRegisterDesc " << TargetName
      << "RegDesc[] = { // Descriptors\n";
-  OS << "  { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
+  OS << "  { " << RegStrings.get("") << ", " << RegAsmStrings.get("")
+     << ", 0, 0, 0, 0, 0 },\n";
 
   // Emit the register descriptors now.
   i = 0;
   for (const auto &Reg : Regs) {
     OS << "  { " << RegStrings.get(Reg.getName()) << ", "
+       << RegAsmStrings.get(Reg.getAsmName()) << ", "
        << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
        << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
        << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", "
        << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n";
     ++i;
   }
   OS << "};\n\n";      // End of register descriptors...
 
OS << "static inline void Init" << TargetName
      << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
      << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
         "{\n"
      << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
      << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
      << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
-     << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
+     << TargetName << "RegAsmStrings, " << TargetName << "RegClassStrings, "
+     << TargetName << "SubRegIdxLists, "
      << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
      << TargetName << "SubRegIdxRanges, " << TargetName
      << "RegEncodingTable);\n\n";
 
   EmitRegMapping(OS, Regs, false);
 
   OS << "}\n\n";
 
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
 
   EmitRegUnitPressure(OS, RegBank, ClassName);
 
   // Emit the constructor of the class...
   OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
   OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
   OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n";
   OS << "extern const char " << TargetName << "RegStrings[];\n";
+  OS << "extern const char " << TargetName << "RegAsmStrings[];\n";
   OS << "extern const char " << TargetName << "RegClassStrings[];\n";
   OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
   OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
   OS << "extern const MCRegisterInfo::SubRegCoveredBits "
      << TargetName << "SubRegIdxRanges[];\n";
   OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
 
   EmitRegMappingTables(OS, Regs, true);
 
   OS << ClassName << "::\n" << ClassName
      << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
      << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
      << "             SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
   OS.write_hex(RegBank.CoveringLanes);
   OS << ") {\n"
      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
      << ", RA, PC,\n                     " << TargetName
      << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
      << "                     " << TargetName << "RegUnitRoots,\n"
      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"
      << "                     " << TargetName << "RegDiffLists,\n"
      << "                     " << TargetName << "LaneMaskLists,\n"
      << "                     " << TargetName << "RegStrings,\n"
+     << "                     " << TargetName << "RegAsmStrings,\n"
      << "                     " << TargetName << "RegClassStrings,\n"
      << "                     " << TargetName << "SubRegIdxLists,\n"
      << "                     " << SubRegIndicesSize + 1 << ",\n"
      << "                     " << TargetName << "SubRegIdxRanges,\n"
      << "                     " << TargetName << "RegEncodingTable);\n\n";
 
   EmitRegMapping(OS, Regs, true);