Index: include/llvm/Object/RelocVisitor.h
===================================================================
--- include/llvm/Object/RelocVisitor.h
+++ include/llvm/Object/RelocVisitor.h
@@ -140,6 +140,14 @@
           HasError = true;
           return RelocToApply();
         }
+      case Triple::amdgcn:
+        switch (RelocType) {
+        case llvm::ELF::R_AMDGPU_32_LOW:
+          return visitELF_AMDGPU_32_LOW(R, Value);
+        default:
+          HasError = true;
+          return RelocToApply();
+        }
       default:
         HasError = true;
         return RelocToApply();
@@ -404,6 +412,13 @@
     return RelocToApply(static_cast<uint32_t>(Res), 4);
   }
 
+  /// AMDGPU ELF
+  RelocToApply visitELF_AMDGPU_32_LOW(RelocationRef R, uint64_t Value) {
+    int64_t Addend = getELFAddend(R);
+    uint32_t Res = (Value + Addend) & 0xFFFFFFFF;
+    return RelocToApply(Res, 4);
+  }
+
   /// I386 COFF
   RelocToApply visitCOFF_I386_SECREL(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
Index: include/llvm/Support/ELF.h
===================================================================
--- include/llvm/Support/ELF.h
+++ include/llvm/Support/ELF.h
@@ -614,6 +614,11 @@
 #include "ELFRelocs/WebAssembly.def"
 };
 
+// ELF Relocation types for AMDGPU
+enum {
+#include "ELFRelocs/AMDGPU.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.
Index: include/llvm/Support/ELFRelocs/AMDGPU.def
===================================================================
--- include/llvm/Support/ELFRelocs/AMDGPU.def
+++ include/llvm/Support/ELFRelocs/AMDGPU.def
@@ -0,0 +1,9 @@
+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AMDGPU_NONE,    0)
+ELF_RELOC(R_AMDGPU_32_LOW,  1)
+ELF_RELOC(R_AMDGPU_32_HIGH, 2)
+ELF_RELOC(R_AMDGPU_64,      3)
Index: lib/MC/MCObjectFileInfo.cpp
===================================================================
--- lib/MC/MCObjectFileInfo.cpp
+++ lib/MC/MCObjectFileInfo.cpp
@@ -425,6 +425,11 @@
       TTypeEncoding = dwarf::DW_EH_PE_absptr;
     }
     break;
+  case Triple::amdgcn:
+    LSDAEncoding = dwarf::DW_EH_PE_absptr;
+    PersonalityEncoding = dwarf::DW_EH_PE_absptr;
+    TTypeEncoding = dwarf::DW_EH_PE_absptr;
+    break;
   default:
     break;
   }
Index: lib/Object/ELF.cpp
===================================================================
--- lib/Object/ELF.cpp
+++ lib/Object/ELF.cpp
@@ -105,6 +105,12 @@
       break;
     }
     break;
+  case ELF::EM_AMDGPU:
+    switch (Type) {
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    default:
+      break;
+    }
   default:
     break;
   }
Index: lib/ObjectYAML/ELFYAML.cpp
===================================================================
--- lib/ObjectYAML/ELFYAML.cpp
+++ lib/ObjectYAML/ELFYAML.cpp
@@ -531,6 +531,9 @@
   case ELF::EM_LANAI:
 #include "llvm/Support/ELFRelocs/Lanai.def"
     break;
+  case ELF::EM_AMDGPU:
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -11,6 +11,7 @@
 #include "AMDGPUMCTargetDesc.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCValue.h"
 
 using namespace llvm;
 
@@ -21,10 +22,7 @@
   AMDGPUELFObjectWriter(bool Is64Bit);
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                        const MCFixup &Fixup, bool IsPCRel) const override {
-    return Fixup.getKind();
-  }
-
+                        const MCFixup &Fixup, bool IsPCRel) const override;
 };
 
 
@@ -32,7 +30,26 @@
 
 AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit)
   : MCELFObjectTargetWriter(Is64Bit, ELF::ELFOSABI_AMDGPU_HSA,
-                            ELF::EM_AMDGPU, false) { }
+                            ELF::EM_AMDGPU, true) { }
+
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
+                                             const MCValue &Target,
+                                             const MCFixup &Fixup,
+                                             bool IsPCRel) const {
+  MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
+  switch (Modifier) {
+  case MCSymbolRefExpr::VK_None:
+    switch (Fixup.getKind()) {
+    case FK_Data_4:
+      return ELF::R_AMDGPU_32_LOW;
+    default:
+      break;
+    }
+  default:
+    break;
+  }
+  llvm_unreachable("unhandled relocation type");
+}
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter(Is64Bit);
Index: test/Object/AMDGPU/elf64-reloc-visit.test
===================================================================
--- test/Object/AMDGPU/elf64-reloc-visit.test
+++ test/Object/AMDGPU/elf64-reloc-visit.test
@@ -0,0 +1,9 @@
+RUN: llvm-dwarfdump -debug-dump=info %p/../Inputs/elf64-amdgpu-reloc-visit.o 2>&1 | FileCheck %s
+
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000005b] = "reloc_visit1")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000068] = "reloc_visit2")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000082] = "A")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000075] = "reloc_visit3")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000088] = "B")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000084] = "int")
+CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x0000008a] = "unsigned int")
Index: test/Object/AMDGPU/elf64-relocs.yaml
===================================================================
--- test/Object/AMDGPU/elf64-relocs.yaml
+++ test/Object/AMDGPU/elf64-relocs.yaml
@@ -0,0 +1,53 @@
+# RUN: yaml2obj -format=elf %s > %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# CHECK: Relocations [
+# CHECK:   Section (2) .rel.text {
+# CHECK:     0x0 R_AMDGPU_NONE main 0x0
+# CHECK:     0x8 R_AMDGPU_32_LOW - 0x0
+# CHECK:     0x10 R_AMDGPU_32_HIGH - 0x0
+# CHECK:     0x18 R_AMDGPU_64 - 0x0
+# CHECK:   }
+# CHECK: ]
+
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_AMDGPU
+Sections:
+  - Type:            SHT_PROGBITS
+    Name:            .text
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x08
+    Content:         0000000000000000
+  - Type:            SHT_REL
+    Name:            .rel.text
+    Link:            .symtab
+    Info:            .text
+    AddressAlign:    0x08
+    Relocations:
+      - Offset:          0x0
+        Symbol:          main
+        Type:            R_AMDGPU_NONE
+      - Offset:          0x8
+        Symbol:          a
+        Type:            R_AMDGPU_32_LOW
+      - Offset:          0x10
+        Symbol:          b
+        Type:            R_AMDGPU_32_HIGH
+      - Offset:          0x18
+        Symbol:          c
+        Type:            R_AMDGPU_64
+
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+
+  Global:
+    - Name:            main
+      Type:            STT_FUNC
+      Section:         .text
+      Size:            0x08