Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1409,6 +1409,20 @@
   if (isLdStPairSuppressed(MI))
     return false;
 
+  // Do not pair quad ld/st for Exynos.
+  if (Subtarget.isExynosM1()) {
+      switch (MI->getOpcode()) {
+        default:
+          break;
+
+        case AArch64::LDURQi:
+        case AArch64::STURQi:
+        case AArch64::LDRQui:
+        case AArch64::STRQui:
+          return false;
+        }
+    }
+
   return true;
 }
 
Index: llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -1,5 +1,6 @@
 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
 
 ; Test ldr clustering.
 ; CHECK: ********** MI Scheduling **********
@@ -97,3 +98,18 @@
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
+
+; Test no ldq clustering for Exynos.
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: exynos_ldq_no_cluster:BB#0
+; EXYNOS-NOT: Cluster loads
+define <2 x i64> @exynos_ldq_no_cluster(i64* %p) {
+  %a1 = bitcast i64* %p to <2 x i64>*
+  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
+  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
+  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
+  %tmp2 = mul nsw <2 x i64> %tmp1, %tmp1
+  %tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8
+  %res  = add nsw <2 x i64> %tmp2, %tmp3
+  ret <2 x i64> %res
+}
Index: llvm/test/CodeGen/AArch64/exynos-quad-ldp-stp.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/exynos-quad-ldp-stp.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
+
+; CHECK-LABEL: test_exynos_nopair_st
+; CHECK: str
+; CHECK: stur
+; CHECK-NOT: stp
+define void @test_exynos_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
+  %tmp1 = bitcast double* %ptr to <2 x double>*
+  store <2 x double> %v2, <2 x double>* %tmp1, align 16
+  %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
+  %tmp = bitcast double* %add.ptr to <2 x double>*
+  store <2 x double> %v1, <2 x double>* %tmp, align 16
+  ret void
+}
+
+; CHECK-LABEL: test_exynos_nopair_ld
+; CHECK: ldr
+; CHECK: ldr
+; CHECK-NOT: ldp
+define <2 x i64> @test_exynos_nopair_ld(i64* %p) {
+  %a1 = bitcast i64* %p to <2 x i64>*
+  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
+  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
+  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
+  %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
+  %add = add nsw <2 x i64> %tmp1, %tmp2
+  ret <2 x i64> %add
+}