Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -2077,11 +2077,12 @@ class TLB : InstSE<(outs), (ins), asmstr, [], NoItinerary, FrmOther, asmstr>; -def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; -def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; -def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; -def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; - +let AdditionalPredicates = [NotInMicroMips] in { + def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; + def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; + def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; + def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; +} class CacheOp : InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -298,3 +298,7 @@ 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 +0x00 0x00 0x03 0x7c # CHECK: tlbp +0x00 0x00 0x13 0x7c # CHECK: tlbr +0x00 0x00 0x23 0x7c # CHECK: tlbwi +0x00 0x00 0x33 0x7c # CHECK: tlbwr Index: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -225,3 +225,7 @@ 0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5 0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5 +0x00 0x00 0x03 0x7c # CHECK: tlbp +0x00 0x00 0x13 0x7c # CHECK: tlbr +0x00 0x00 0x23 0x7c # CHECK: tlbwi +0x00 0x00 0x33 0x7c # CHECK: tlbwr Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -137,3 +137,15 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction Index: llvm/trunk/test/MC/Mips/micromips32r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s @@ -309,3 +309,7 @@ mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] + tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] + tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] + tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] + tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] Index: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s @@ -162,3 +162,15 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction Index: llvm/trunk/test/MC/Mips/micromips64r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s @@ -220,5 +220,9 @@ daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f] dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb] dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb] + tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] + tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] + tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] + tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] 1: